Abstract: A controllable precision delay line implemented in a digital integrated circuit device including a counter circuit for measuring a representative propagation delay for a delay element in the digital integrated circuit, and a binary controlled digital delay line responsive to the counter circuit and including L delay stages respectively having 2.sup.0 through 2.sup.L-1 delay elements, wherein the delay stages are controllably switched into a delay path pursuant to the measured representative propagation delay. Preload connections are provided between the outputs of delay elements of stages S(0) through S(L-2) and inputs of delay elements of the next in sequence stages S(1) through S(L-1) to prevent glitches being imposed on the delayed signal during adjustments in the number of stages included in the delay path.

Abstract: A programmable hold-off circuit for an integrated circuit for selectively providing hold-off for outputs of the integrated circuit. The programmable hold-off circuit includes a hold-off latch for receiving an output signal from the interior logic of the integrated circuit, and for providing a hold-off latch output, an output buffer responsive to hold-off latch output for providing a buffered output, a hold-off control circuit responsive to a hold clock for controlling the hold-off latch to be continuously transparent when the hold-off control circuit is programmed for no hold-off, and for controlling the hold-off latch pursuant to the hold clock when the hold-off control circuit is programmed for hold-off. The hold-off control circuit is programmed, for example, pursuant to a boundary scan flip-flop.

Abstract: A burn-in heating circuit for an integrated circuit including a burn-in clock generator for producing a burn-in clock signal that is provided to the clock buffer of the clock distribution system of the integrated circuit. The operating frequency of the burn-in clock is at or close to the maximum frequency that the clock distribution system can reliably sustain with valid logic levels, so that the highest possible self-heating can be achieved by power dissipation in the clock distribution system. A comparator that is responsive to a temperature signal representative of the integrated circuit junction temperature and a signal indicative of the desired burn-in temperature modulates the clock generator so that the junction temperature of the integrated circuit resulting from self heating is close to the desired burn-in temperature.