Patents by Inventor Bradley W. Scheer

Bradley W. Scheer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6646737
    Abstract: A calibration standard which may be used to calibrate lateral dimensional measurement systems is provided. The calibration standard may include a first substrate spaced from a second substrate. In addition, the calibration standard may include at least one layer disposed between the first and second substrates. The layer may have a traceably measured thickness. For example, a thickness of the layer may be traceably measured using any measurement technique in which a measurement system may be calibrated with a standard reference material traceable to a national testing authority. The calibration standard may be cross-sectioned in a direction substantially perpendicular to an upper surface of the first substrate. The cross-sectioned portion of the calibration standard may form a viewing surface of the calibration standard. In this manner, a lateral dimensional artifact of the calibration standard may include the traceably measured thickness of at least the one layer.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: November 11, 2003
    Assignee: KLA-Tencor Technologies
    Inventors: Marco Tortonese, Ian Smith, Ellen Laird, Bradley W. Scheer
  • Publication number: 20030058437
    Abstract: A calibration standard which may be used to calibrate lateral dimensional measurement systems is provided. The calibration standard may include a first substrate spaced from a second substrate. In addition, the calibration standard may include at least one layer disposed between the first and second substrates. The layer may have a traceably measured thickness. For example, a thickness of the layer may be traceably measured using any measurement technique in which a measurement system may be calibrated with a standard reference material traceable to a national testing authority. The calibration standard may be cross-sectioned in a direction substantially perpendicular to an upper surface of the first substrate. The cross-sectioned portion of the calibration standard may form a viewing surface of the calibration standard. In this manner, a lateral dimensional artifact of the calibration standard may include the traceably measured thickness of at least the one layer.
    Type: Application
    Filed: September 24, 2001
    Publication date: March 27, 2003
    Inventors: Marco Tortonese, Ian Smith, Ellen Laird, Bradley W. Scheer
  • Patent number: 6358860
    Abstract: A method of making and certifying submicron line width calibration standards includes steps of thermal growth of a silicon dioxide film layer on top and vertical side wall surfaces of silicon regions, e.g. strips or mounds, that are formed over a silicon dioxide layer on a silicon substrate, then optically measuring the top film layer thickness, removing the oxide film from the top surface of the silicon regions via a planarization technique that protects the film on the side walls, and finally removing at least some, and in most cases preferably all, of the silicon material to leave just the oxide film that was on the side walls of the former silicon regions as submicron linear features, such as extended isolated lines or connected line segments arranged in a polygon.
    Type: Grant
    Filed: February 2, 2000
    Date of Patent: March 19, 2002
    Assignee: VLSI Standards, Inc.
    Inventors: Bradley W. Scheer, Ellen R. Laird
  • Patent number: 6016684
    Abstract: An atomic-level step-height standard with step heights less than about 100 .ANG. is in the form of a silicon wafer die with a generally smooth reflective surface but with a periodic pattern of alternating parallel flat linear mesas and valleys having a rectangular cross-section. The periodicity of this pattern of surface features is less than 100 .mu.m and preferably about 20 .mu.m. Certification of the standard involves measuring the pitch and the line or space width of the mesas or valleys using a calibrated probe microscope in order to determine the pattern's duty cycle (C), and also measuring a bidirectional reflectance distribution function for light scattered from the periodic pattern using an angle-resolved scatterometer. From this measurement, a one-dimensional power spectral density function is calculated, then an RMS roughness (R.sub.q) value is derived. The characteristic step height (H) of the standard can then be certified as being H=R.sub.q [C(1-C)].sup.
    Type: Grant
    Filed: March 10, 1998
    Date of Patent: January 25, 2000
    Assignee: VLSI Standards, Inc.
    Inventors: Bradley W. Scheer, J. Jerry Prochazka
  • Patent number: 5955654
    Abstract: A metrology standard that is useful for calibrating instruments for the levels of microroughness encountered in semiconductor, disk drive, and related industries today. In advanced applications, this level is about 5 .ANG. rms in a 0.01-1.0 .mu.m.sup.-1 spatial bandwidth range. This standard uses a one-dimensional square wave pattern etched in a silicon wafer to reduce the effects of instrument spatial bandwidth. The standard has approximately a 20 .mu.m pitch with feature depths as small as 8 .ANG..
    Type: Grant
    Filed: August 7, 1997
    Date of Patent: September 21, 1999
    Assignee: VLSI Standards, Inc.
    Inventors: John C. Stover, Bradley W. Scheer
  • Patent number: 5677765
    Abstract: A method for calibrating topographic instruments, operating at sub-micrometer resolution levels, includes providing a calibration standard having a known one-dimensional power spectral density function. A roughness is calculated from the known one dimensional power spectral density function in relation to an atomic scale topographic dimension, .increment.z.sub.i. The roughness of the calibration standard is measured by detecting light scattering therefrom and computing an isotropic power spectral density curve over the effective spatial bandwidth of the topographic instrument being calibrated. The measured roughness is then compared against the calculated roughness to determine whether the two values of roughness coincide.
    Type: Grant
    Filed: August 16, 1996
    Date of Patent: October 14, 1997
    Assignee: VLSI Standards, Inc.
    Inventors: Ellen R. Laird, W. Murray Bullis, James J. Greed, Jr., Bradley W. Scheer
  • Patent number: 5659388
    Abstract: A condensation nucleus counter includes a saturator and a condenser with a thermoelectric device (TED) to simultaneously cool the condenser and heat the saturator. A controller is featured which operates the TED to maintain the temperature differential between the saturator and the condenser to within .+-.1.5.degree. C. at steady state. The controller may be set by a user to operate at any desired setpoint temperature.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: August 19, 1997
    Assignee: VLSI Standards, Inc.
    Inventors: Craig A. Scheer, Bradley W. Scheer
  • Patent number: 5599464
    Abstract: A calibration target for topographic inspection instruments, operating at sub-micrometer resolution levels, having features on the order of 10 Angstroms in vertical height, an atomic scale distance. The features are formed on a silicon substrate, such as a wafer, by deposition of a thick oxide, such as a typical thermal oxide, over the wafer surface. A pattern of features is patterned and etched to the level of raw silicon at the wafer surface. Areas which have been etched are converted to a thin oxide, which slightly lowers the level of silicon in these areas. All oxide is removed and the slightly lower level of silicon gives rise to features having atomic scale vertical topographic dimensions. Millions of such features are produced simultaneously on a wafer to mimic the effect of haze or micro-roughness on a polished wafer.
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: February 4, 1997
    Assignee: VLSI Standards, Inc.
    Inventors: Ellen R. Laird, W. Murray Bullis, James J. Greed, Jr., Bradley W. Scheer
  • Patent number: 5198869
    Abstract: A standard for calibrating a wafer surface inspection optical scanner, particularly a system for measuring haze. The referene wafer contains sections divided into subsections, each subsection having a quasi-random pattern of light scattering features on an otherwise polished surface of the wafer. The quasi-random pattern of features is formed by creating a random pattern of pits within tiny areas of the subsection and repeating that pattern. The random pattern of pits covers an area less than the area of the spot of a scanning beam used by the wafer surface inspection system. By randomizing the pattern of pits within the scanning beam, the scattered light does not produce interference patterns and thus the scattered light is more isotropic. A direct measurement of the amount of hazel on the reference wafer can be obtained from measuring the amount of scattered light caused by the pits.
    Type: Grant
    Filed: October 15, 1990
    Date of Patent: March 30, 1993
    Assignee: VLSI Standards, Inc.
    Inventors: Robert J. Monteverde, Bradley W. Scheer
  • Patent number: 5194297
    Abstract: A particle deposition system having an atomizer, wafer transport, sheath flow means, particle counter and computer control for accurately depositing a desired density of particles onto a surface. The sheath flow keeps an article clean, while the particle flux in the deposition chamber is rising from zero to an equilibrium state. The particle counter measures particle flux by sampling the atmosphere in the deposition chamber. The computer determines when the rate of change of particle flux is substantially zero and then actuates transport of the article completely or partially out of the sheath flow into the mist of falling particles. The computer also calculates the required deposition time for providing the article's surface with a desired particle density, actuating transport of the article back into the sheath flow after the desired density is reached. The operator of the system can specify particle size, desired density and full or partial coverage of the surface with particles.
    Type: Grant
    Filed: March 4, 1992
    Date of Patent: March 16, 1993
    Assignee: VLSI Standards, Inc.
    Inventors: Bradley W. Scheer, Paul A. Konicek
  • Patent number: 5078492
    Abstract: A patterned wafer for testing an optical scanner. The wafer has standard size light scattering features, such as pits, distributed in aligned groups arranged in annular bands about a concentric center. Empty annular bands separate the feature containing annular bands. The empty bands simulate wafer edges for various size wafers. In this manner, wafer edges may be excluded in a particle count for a predetermined size wafer. Apparent size variations in multiple scans indicate misalignments relative to the scan center.
    Type: Grant
    Filed: June 17, 1991
    Date of Patent: January 7, 1992
    Assignee: VLSI Standards, Inc.
    Inventor: Bradley W. Scheer