Patents by Inventor Brennan L. Peterson

Brennan L. Peterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8278718
    Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: October 2, 2012
    Assignee: Intel Corporation
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Publication number: 20120068273
    Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.
    Type: Application
    Filed: November 29, 2011
    Publication date: March 22, 2012
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Patent number: 8120119
    Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: February 21, 2012
    Assignee: Intel Corporation
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Patent number: 7968952
    Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: June 28, 2011
    Assignee: Intel Corporation
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Publication number: 20110133259
    Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.
    Type: Application
    Filed: February 15, 2011
    Publication date: June 9, 2011
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Patent number: 7719062
    Abstract: A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a portion of the slot contact opening in order to induce a tensile stress on an adjacent channel region. The remainder of the slot contact opening is filled with a lower resistivity contact metal. Barrier plug deposition temperature can be varied in order to tune the tensile stress on the adjacent channel region.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Patent number: 7605469
    Abstract: Apparatus and methods of fabricating an atomic layer deposited tantalum containing adhesion layer within at least one dielectric material in the formation of a metal, wherein the atomic layer deposition tantalum containing adhesion layer is sufficiently thin to minimize contact resistance and maximize the total cross-sectional area of metal, including but not limited to tungsten, within the contact.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: October 20, 2009
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Kerry Spurgin, Brennan L. Peterson
  • Patent number: 7601637
    Abstract: Apparatus and methods of fabricating an atomic layer deposited tantalum containing adhesion layer within at least one dielectric material in the formation of a metal, wherein the atomic layer deposition tantalum containing adhesion layer is sufficiently thin to minimize contact resistance and maximize the total cross-sectional area of metal, including but not limited to tungsten, within the contact.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: October 13, 2009
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Kerry Spurgin, Brennan L. Peterson
  • Patent number: 7582558
    Abstract: Copper interconnects may be made using the damascene process with reduced copper corrosion. Copper corrosion may be reduced by planarizing through excess copper down to, but not completely through, a copper diffusion barrier layer. The copper diffusion barrier layer may be removed using a different technique. Thereafter, suitable chemicals may be utilized to clean the structure.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: September 1, 2009
    Assignee: Intel Corporation
    Inventors: Vinay B. Chikarmane, Kevin J. Fischer, Brennan L. Peterson
  • Publication number: 20090155998
    Abstract: Apparatus and methods of fabricating an atomic layer deposited tantalum containing adhesion layer within at least one dielectric material in the formation of a metal, wherein the atomic layer deposition tantalum containing adhesion layer is sufficiently thin to minimize contact resistance and maximize the total cross-sectional area of metal, including but not limited to tungsten, within the contact.
    Type: Application
    Filed: December 24, 2008
    Publication date: June 18, 2009
    Inventors: Steven W. Johnston, Kerry Spurgin, Brennan L. Peterson
  • Publication number: 20080157208
    Abstract: A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Publication number: 20080157224
    Abstract: A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a portion of the slot contact opening in order to induce a tensile stress on an adjacent channel region. The remainder of the slot contact opening is filled with a lower resistivity contact metal. Barrier plug deposition temperature can be varied in order to tune the tensile stress on the adjacent channel region.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Kevin J. Fischer, Vinay B. Chikarmane, Brennan L. Peterson
  • Publication number: 20080076246
    Abstract: Embodiments of the invention include apparatuses and methods relating to through contact-opening silicide and barrier layer formation. In one embodiment, a silicide region is formed in a silicon substrate by deposition of a siliciding material in a contact opening and a subsequent anneal.
    Type: Application
    Filed: September 25, 2006
    Publication date: March 27, 2008
    Inventors: Brennan L. Peterson, Vinay B. Chikarmane, Kevin J. Fischer
  • Publication number: 20080014746
    Abstract: Copper interconnects may be made using the damascene process with reduced copper corrosion. Copper corrosion may be reduced by planarizing through excess copper down to, but not completely through, a copper diffusion barrier layer. The copper diffusion barrier layer may be removed using a different technique. Thereafter, suitable chemicals may be utilized to clean the structure.
    Type: Application
    Filed: July 14, 2006
    Publication date: January 17, 2008
    Inventors: Vinay B. Chikarmane, Kevin J. Fischer, Brennan L. Peterson