Patents by Inventor Brennen Mueller

Brennen Mueller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098387
    Abstract: Composite integrated circuit (IC) device structures that include two components coupled through a hybrid bonded composite interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over substantially planar dielectric and metallization interfaces. Composite interconnect metallization features formed at a bond interface may be doped with a metal or chalcogenide dopant. The dopant may migrate to a periphery of the composite interconnect structure and form a barrier material that will then limit outdiffusion of a metal, such as copper, into adjacent dielectric material.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Applicant: Intel Corporation
    Inventors: Carl Naylor, Mauro Kobrinsky, Richard Vreeland, Ramanan Chebiam, William Brezinski, Brennen Mueller, Jeffery Bielefeld
  • Publication number: 20210098360
    Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Applicant: Intel Corporation
    Inventors: Manish Chandhok, Ramanan Chebiam, Brennen Mueller, Colin Carver, Jeffery Bielefeld, Nafees Kabir, Richard Vreeland, William Brezinski
  • Publication number: 20200303191
    Abstract: Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 24, 2020
    Inventors: Anant JAHAGIRDAR, Chytra PAWASHE, Aaron LILAK, Myra MCDONNELL, Brennen MUELLER, Mauro KOBRINSKY
  • Publication number: 20200273839
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.
    Type: Application
    Filed: December 29, 2017
    Publication date: August 27, 2020
    Inventors: Adel A. ELSHERBINI, Henning BRAUNISCH, Aleksandar ALEKSOV, Shawna M. LIFF, Johanna M. SWAN, Patrick MORROW, Kimin JUN, Brennen MUELLER, Paul B. FISCHER
  • Publication number: 20200235061
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 23, 2020
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Patrick Morrow, Henning Braunisch, Kimin Jun, Brennen Mueller, Shawna M. Liff, Johanna M. Swan, Paul B. Fischer
  • Publication number: 20200211905
    Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor stacked above and self-aligned with a second transistor, where a shadow of the first transistor substantially overlaps with the second transistor. The first transistor includes a first gate electrode, a first channel layer including a first channel material and separated from the first gate electrode by a first gate dielectric layer, and a first source electrode coupled to the first channel layer. The second transistor includes a second gate electrode, a second channel layer including a second channel material and separated from the second gate electrode by a second gate dielectric layer, and a second source electrode coupled to the second channel layer. The second source electrode is self-aligned with the first source electrode, and separated from the first source electrode by an isolation layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Cheng-Ying HUANG, Willy RACHMADY, Gilbert DEWEY, Aaron LILAK, Kimin JUN, Brennen MUELLER, Ehren MANNEBACH, Anh PHAN, Patrick MORROW, Hui Jae YOO, Jack T. KAVALIEROS
  • Publication number: 20200212038
    Abstract: An integrated circuit structure comprises a substrate and a stacked channel of self-aligned heterogeneous materials, wherein the stacked channel of self-aligned heterogeneous materials comprises an NMOS channel material over the substrate; and a PMOS channel material stacked over and self-aligned with the NMOS channel material. A heterogeneous gate stack is in contact the both the NMOS channel material and the PMOS channel material.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Willy RACHMADY, Aaron LILAK, Brennen MUELLER, Hui Jae YOO, Patrick MORROW, Anh PHAN, Cheng-Ying HUANG, Ehren MANNEBACH, Kimin JUN, Gilbert DEWEY
  • Publication number: 20200194570
    Abstract: Embodiments herein describe techniques for a semiconductor device over a semiconductor substrate. A first bonding layer is above the semiconductor substrate. One or more nanowires are formed above the first bonding layer to be a channel layer. A gate electrode is around a nanowire, where the gate electrode is in contact with the first bonding layer and separated from the nanowire by a gate dielectric layer. A source electrode or a drain electrode is in contact with the nanowire, above a bonding area of a second bonding layer, and separated from the gate electrode by a spacer, where the second bonding layer is above and in direct contact with the first bonding layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Kimin Jun, Jack T. Kavalieros, Gilbert Dewey, Willy Rachmady, Aaron Lilak, I, Brennen Mueller, Hui Jae Yoo, Patrick Morrow, Anh Phan, Cheng-Ying Huang, Ehren Mannebach
  • Publication number: 20130196019
    Abstract: The present invention describes the synthesis of silicon-containing monomers and copolymers. The synthesis of a monomer, trimethyl-(2-methylenebut-3-enyl)silane (TMSI) and subsequent synthesis of diblock copolymer with styrene, forming polystyrene-block-polytrimethylsilyl isoprene, and synthesis of diblock copolymer Polystyrene-block-polymethacryloxymethyltrimethylsilane or PS-b-P(MTMSMA). These silicon containing diblock copolymers have a variety of uses. One preferred application is as novel imprint template material with sub-100 nm features for lithography.
    Type: Application
    Filed: March 17, 2011
    Publication date: August 1, 2013
    Applicant: National University of Sinapore
    Inventors: C. Grant Willson, Christopher M. Bates, Jeffrey Strahan, Christopher John Ellison, Brennen Mueller