Patents by Inventor Brent Alan Anderson
Brent Alan Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11710666Abstract: A technique relates to a semiconductor device. A source/drain layer is formed. Fins with gate stacks are formed in a fill material, a dummy fin template including at least one fin of the fins and at least one gate stack of the gate stacks, the fins being formed on the source/drain layer. A trench is formed through the fill material by removing the dummy fin template, such that a portion of the source/drain layer is exposed in the trench. A source/drain metal contact is formed on the portion of the source/drain layer in the trench.Type: GrantFiled: June 30, 2021Date of Patent: July 25, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Junli Wang, Brent Alan Anderson, Albert Young
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Patent number: 11670542Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having stepped top vias that reduce via resistance. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a first dielectric layer. A second dielectric layer is formed on the recessed surface and an etch stop layer is formed over the structure. A first cavity is formed that exposes the recessed surface of the conductive line and sidewalls of the second dielectric layer. The first cavity includes a first width between sidewalls of the etch stop layer. The second dielectric layer is removed to define a second cavity having a second width greater than the first width. A stepped top via is formed on the recessed surface of the conductive line. The top via includes a top portion in the first cavity and a bottom portion in the second cavity.Type: GrantFiled: January 7, 2022Date of Patent: June 6, 2023Assignee: International Business Machines CorporationInventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
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Patent number: 11600565Abstract: A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line, each disposed in a first dielectric layer and extending from the first etch stop layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer comprising a second dielectric layer disposed on a top surface of the first metallization layer and a first via and a second via in the second dielectric layer. The semiconductor structure further includes a first conductive material disposed on a top surface of the first conductive line in the first via. The semiconductor structure further includes a second conductive material disposed on a top surface of the second conductive line in the second via.Type: GrantFiled: October 7, 2021Date of Patent: March 7, 2023Assignee: International Business Machines CorporationInventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
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Publication number: 20220359394Abstract: Integrated chips include first lines, formed on an underlying substrate. Spacers are formed conformally on sidewalls of the plurality of lines. Etch stop remnants are positioned on the sidewalls of the plurality of lines, between the spacers and the underlying substrate. Second lines are formed on the underlying substrate, between respective pairs of adjacent first lines.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
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Patent number: 11437317Abstract: Integrated chips and methods of forming lines in the same include forming first lines on a underlying substrate. Conformal dielectric spacers are formed on sidewalls of the first lines. Second lines are formed on the underlying substrate, in open areas between the dielectric spacers.Type: GrantFiled: February 10, 2020Date of Patent: September 6, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
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Patent number: 11430735Abstract: A multi-layer device comprising a barrier or adhesion layer located on a portion of a first top surface of a first layer, a conductive metal layer located on barrier or adhesion layer; and a dielectric layer located on top of the first layer, wherein the dielectric layer is in direct contact with the sidewall of the conductive metal layer.Type: GrantFiled: February 14, 2020Date of Patent: August 30, 2022Assignee: International Business Machines CorporationInventors: Brent Alan Anderson, Nicholas Anthony Lanzillo, Christopher J. Penny, Lawrence A. Clevenger, Kisik Choi, Robert Robison
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Publication number: 20220130718Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having stepped top vias that reduce via resistance. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a first dielectric layer. A second dielectric layer is formed on the recessed surface and an etch stop layer is formed over the structure. A first cavity is formed that exposes the recessed surface of the conductive line and sidewalls of the second dielectric layer. The first cavity includes a first width between sidewalls of the etch stop layer. The second dielectric layer is removed to define a second cavity having a second width greater than the first width. A stepped top via is formed on the recessed surface of the conductive line. The top via includes a top portion in the first cavity and a bottom portion in the second cavity.Type: ApplicationFiled: January 7, 2022Publication date: April 28, 2022Inventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
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Publication number: 20220028783Abstract: A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line, each disposed in a first dielectric layer and extending from the first etch stop layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer comprising a second dielectric layer disposed on a top surface of the first metallization layer and a first via and a second via in the second dielectric layer. The semiconductor structure further includes a first conductive material disposed on a top surface of the first conductive line in the first via. The semiconductor structure further includes a second conductive material disposed on a top surface of the second conductive line in the second via.Type: ApplicationFiled: October 7, 2021Publication date: January 27, 2022Inventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
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Patent number: 11232977Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having stepped top vias that reduce via resistance. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a first dielectric layer. A second dielectric layer is formed on the recessed surface and an etch stop layer is formed over the structure. A first cavity is formed that exposes the recessed surface of the conductive line and sidewalls of the second dielectric layer. The first cavity includes a first width between sidewalls of the etch stop layer. The second dielectric layer is removed to define a second cavity having a second width greater than the first width. A stepped top via is formed on the recessed surface of the conductive line. The top via includes a top portion in the first cavity and a bottom portion in the second cavity.Type: GrantFiled: February 11, 2020Date of Patent: January 25, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
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Patent number: 11195792Abstract: A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line disposed in a first dielectric layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer having a second dielectric layer disposed on a top surface of the first metallization layer and a first via in the second dielectric layer. The first via is configured to expose a portion of a top surface of the second conductive line. The semiconductor structure further includes a first conductive material disposed in the first via.Type: GrantFiled: January 10, 2020Date of Patent: December 7, 2021Assignee: International Business Machines CorporationInventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
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Publication number: 20210327766Abstract: A technique relates to a semiconductor device. A source/drain layer is formed. Fins with gate stacks are formed in a fill material, a dummy fin template including at least one fin of the fins and at least one gate stack of the gate stacks, the fins being formed on the source/drain layer. A trench is formed through the fill material by removing the dummy fin template, such that a portion of the source/drain layer is exposed in the trench. A source/drain metal contact is formed on the portion of the source/drain layer in the trench.Type: ApplicationFiled: June 30, 2021Publication date: October 21, 2021Inventors: Junli Wang, Brent Alan Anderson, Albert Young
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Patent number: 11152507Abstract: Techniques regarding one or more VFETs operably coupled to bottom contacts with low electrical resistance are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a vertical field-effect transistor device that can comprise a semiconductor fin positioned on a source/drain region, which can comprise a semiconductor substrate. The apparatus can also comprise a metal contact layer positioned on the source/drain region and at least partially surrounding a base of the semiconductor fin. Further, the metal contact layer can be in electrical communication with the source/drain region.Type: GrantFiled: November 7, 2018Date of Patent: October 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chen Zhang, Tenko Yamashita, Terence B Hook, Brent Alan Anderson
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Patent number: 11145550Abstract: A technique relates to a semiconductor device. A source/drain layer is formed. Fins with gate stacks are formed in a fill material, a dummy fin template including at least one fin of the fins and at least one gate stack of the gate stacks, the fins being formed on the source/drain layer. A trench is formed through the fill material by removing the dummy fin template, such that a portion of the source/drain layer is exposed in the trench. A source/drain metal contact is formed on the portion of the source/drain layer in the trench.Type: GrantFiled: March 5, 2020Date of Patent: October 12, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Junli Wang, Brent Alan Anderson, Albert Young
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Publication number: 20210280474Abstract: A technique relates to a semiconductor device. A source/drain layer is formed. Fins with gate stacks are formed in a fill material, a dummy fin template including at least one fin of the fins and at least one gate stack of the gate stacks, the fins being formed on the source/drain layer. A trench is formed through the fill material by removing the dummy fin template, such that a portion of the source/drain layer is exposed in the trench. A source/drain metal contact is formed on the portion of the source/drain layer in the trench.Type: ApplicationFiled: March 5, 2020Publication date: September 9, 2021Inventors: Junli Wang, Brent Alan Anderson, Albert Young
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Publication number: 20210257308Abstract: A multi-layer device comprising a barrier or adhesion layer located on a portion of a first top surface of a first layer, a conductive metal layer located on barrier or adhesion layer; and a dielectric layer located on top of the first layer, wherein the dielectric layer is in direct contact with the sidewall of the conductive metal layer.Type: ApplicationFiled: February 14, 2020Publication date: August 19, 2021Inventors: Brent Alan Anderson, Nicholas Anthony Lanzillo, Christopher J. Penny, Lawrence A. Clevenger, Kisik Choi
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Publication number: 20210249302Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having stepped top vias that reduce via resistance. In a non-limiting embodiment of the invention, a surface of a conductive line is recessed below a first dielectric layer. A second dielectric layer is formed on the recessed surface and an etch stop layer is formed over the structure. A first cavity is formed that exposes the recessed surface of the conductive line and sidewalls of the second dielectric layer. The first cavity includes a first width between sidewalls of the etch stop layer. The second dielectric layer is removed to define a second cavity having a second width greater than the first width. A stepped top via is formed on the recessed surface of the conductive line. The top via includes a top portion in the first cavity and a bottom portion in the second cavity.Type: ApplicationFiled: February 11, 2020Publication date: August 12, 2021Inventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert ROBISON
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Publication number: 20210249351Abstract: Integrated chips and methods of forming lines in the same include forming first lines on a underlying substrate. Conformal dielectric spacers are formed on sidewalls of the first lines. Second lines are formed on the underlying substrate, in open areas between the dielectric spacers.Type: ApplicationFiled: February 10, 2020Publication date: August 12, 2021Inventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
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Publication number: 20210217696Abstract: A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line disposed in a first dielectric layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer having a second dielectric layer disposed on a top surface of the first metallization layer and a first via in the second dielectric layer. The first via is configured to expose a portion of a top surface of the second conductive line. The semiconductor structure further includes a first conductive material disposed in the first via.Type: ApplicationFiled: January 10, 2020Publication date: July 15, 2021Inventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
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Patent number: 10985073Abstract: A method for fabricating a semiconductor device includes forming a semiconductor structure including a substrate, a first vertical fin and a second vertical fin longitudinally spaced from the first vertical fin with each of the first and second vertical fin having a hardmask cap, and a bottom spacer layer on the substrate. The method further includes forming first and second bottom source/drains within the substrate respectively beneath the first and second vertical fins, forming first and second top source/drains respectively on the first and second vertical fins, forming a vertical oxide pillar between the first and second vertical fins, removing a portion of the oxide pillar to reduce a cross-sectional dimension to define a lower recessed region, and depositing a metal gate material about the first and second vertical fins wherein portions of the metal gate material are disposed within the recessed region of the oxide pillar.Type: GrantFiled: July 8, 2019Date of Patent: April 20, 2021Assignee: International Business Machines CorporationInventors: Ruilong Xie, Wenyu Xu, Brent Alan Anderson, Zuoguang Liu
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Patent number: 10978454Abstract: A semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected to the first VFET, and including a second fin and a second gate formed on the second fin, and a third VFET formed on the substrate and including a third fin, the first gate being formed on the third fin.Type: GrantFiled: January 30, 2020Date of Patent: April 13, 2021Assignee: ELPIS TECHNOLOGIES INC.Inventors: Brent Alan Anderson, Shawn P. Fetterolf, Terence B. Hook