Patents by Inventor Brent Anderson

Brent Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10755017
    Abstract: A computer-implemented method of cell placement is provided. The method includes representing a non-rectangular cell to be placed into a cell row and searching the cell row to identify existing objects that are representative of cells in the cell row that are disposable to share space with the non-rectangular cell. The method further includes determining whether a representation of the non-rectangular cell is fittable into a modified mapping of the existing objects in the cell row and, in an event the representation is fittable into the modified mapping, overlapping the representation over one or more of the portions of the existing objects.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Laura R. Darden, Albert M. Chu, Alexander J. Suess
  • Patent number: 10742218
    Abstract: A semiconductor structure includes a vertical transport logic circuit cell. The vertical transport logic cell includes a first logic gate and at least a second logic gate. The first logic gate includes at least one input terminal and at least one output terminal. The second logic gate includes at least one input terminal and at least one output terminal. One of the input terminal and the output terminal of the first logic gate shares a pitch of the vertical transport logic circuit cell with one of the input terminal and the output terminal of the second logic gate. The first and second logic gates can include the same type or different types of logic functions.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corpoartion
    Inventors: Brent A. Anderson, Albert Chu
  • Patent number: 10739372
    Abstract: A system includes a probe and a transducer. The probe is detachable and includes a mount having an outlet of a first gas path extending through the probe and a protrusion extending away from the mount. The transducer is configured to mate with the mount and includes a sealing feature adjacent an inlet of the second gas path in fluid communication with the first gas path. When the mount of the probe is adjacent the transducer, the protrusion interacts with the sealing feature such that the sealing feature is in an open position to allow air to flow from the first gas path into the second gas path. When the mount of the probe is distant from the transducer, the sealing feature is in a closed position to prevent contaminants from entering the second gas path.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: August 11, 2020
    Assignee: Rosemount Aerospace Inc.
    Inventors: Brian Brent Naslund, Benjamin John Langemo, Matthew Paul Anderson, Andrew Sherman
  • Patent number: 10741544
    Abstract: A method of fabricating a semiconductor device includes forming one or more fins on a substrate. The method includes forming a first active area and a second active area, each including an n-type dopant, on the substrate at opposing ends of the one or more fins. The method further includes forming a third active area including a p-type dopant on the substrate adjacent to the first active area and the second active area.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Huiming Bu, Terence B. Hook, Xuefeng Liu, Junli Wang
  • Patent number: 10734372
    Abstract: A semiconductor structure includes a vertical transport static random-access memory (SRAM) cell having a first active region and a second active region. The first active region and the second active region are linearly arranged in first and second rows, respectively. The first row of the first active region includes a first pull-up transistor, a first pull-down transistor and a first pass gate transistor, and the second row of the second active region includes a second pull-up transistor, a second pull-down transistor and a second pass gate transistor. A first gate region of the first active region extends orthogonal from the first row to the second active region, and a second gate region of the second active region extends orthogonal from the second row to the first active region.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Stuart A. Sieg, Junli Wang
  • Patent number: 10734277
    Abstract: Back end of line metallization structures and processes of fabricating the metallization structures generally include a top via integration scheme. The top via integration scheme integrally forms the via on top of trench. Thus, the via is fully aligned and can be of a desired critical dimension.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Lawrence A. Clevenger, Benjamin D. Briggs, Brent Anderson
  • Patent number: 10727316
    Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Bruce B. Doris, Seong-Dong Kim, Rajasekhar Venigalla
  • Patent number: 10720425
    Abstract: An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Alain Loiseau
  • Patent number: 10714396
    Abstract: The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10714616
    Abstract: A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak
  • Publication number: 20200212220
    Abstract: A semiconductor structure includes a substrate, a bottom source/drain region disposed on a top surface of the substrate, and a plurality of fins disposed over a top surface of the bottom source/drain region. The fins provide vertical transport channels for one or more vertical transport field-effect transistors. The semiconductor structure also includes at least one self-aligned shared contact disposed between an adjacent pair of the plurality of fins. The adjacent pair of the plurality of fins includes a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Inventors: Ruqiang Bao, Brent A. Anderson, ChoongHyun Lee, Hemanth Jagannathan
  • Publication number: 20200211908
    Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a bottom source/drain region disposed over a top surface of a substrate, the fins providing vertical transport channels for a plurality of vertical transport field-effect transistors. The method also includes forming a first gate conductor surrounding a first one of an adjacent pair of the plurality of fins providing a first vertical transport channel for a first vertical transport field-effect transistor, forming a second gate conductor surrounding a second one of the adjacent pair of the plurality of fins providing a second vertical transport channel for a second vertical transport field-effect transistor, and forming at least one shared gate contact to the first gate conductor and the second gate conductor, the at least one shared gate contact being formed at first ends of the adjacent pair of the plurality of fins.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Brent A. Anderson, ChoongHyun Lee
  • Publication number: 20200203527
    Abstract: A vertical transport fin field effect transistor (VTFET) with a smaller cross-sectional area at the top of the fin than at the bottom, including, a substrate, a vertical fin on the substrate, wherein the vertical fin has a cross-sectional area at the base of the vertical fin that is larger than a cross-sectional area at the top of the vertical fin, wherein the cross-sectional area at the top of the vertical fin is in the range of about 10% to about 75% of the cross-sectional area at the base of the vertical fin, and a central gated region between the base and the top of the vertical fin.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 25, 2020
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10672670
    Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a bottom source/drain region disposed over a top surface of a substrate, the fins providing vertical transport channels for a plurality of vertical transport field-effect transistors. The method also includes forming a first gate conductor surrounding a first one of an adjacent pair of the plurality of fins providing a first vertical transport channel for a first vertical transport field-effect transistor, forming a second gate conductor surrounding a second one of the adjacent pair of the plurality of fins providing a second vertical transport channel for a second vertical transport field-effect transistor, and forming at least one shared gate contact to the first gate conductor and the second gate conductor, the at least one shared gate contact being formed at first ends of the adjacent pair of the plurality of fins.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Brent A. Anderson, ChoongHyun Lee
  • Patent number: 10672905
    Abstract: A semiconductor structure includes a substrate, a bottom source/drain region disposed on a top surface of the substrate, and a plurality of fins disposed over a top surface of the bottom source/drain region. The fins provide vertical transport channels for one or more vertical transport field-effect transistors. The semiconductor structure also includes at least one self-aligned shared contact disposed between an adjacent pair of the plurality of fins. The adjacent pair of the plurality of fins includes a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Brent A. Anderson, ChoongHyun Lee, Hemanth Jagannathan
  • Publication number: 20200166738
    Abstract: A head-mounted display may include a display system and an optical system in a housing. The display system may have a pixel array that produces light associated with images. The display system may also have a linear polarizer through which light from the pixel array passes and a quarter wave plate through which the light passes after passing through the quarter wave plate. The optical system may be a catadioptric optical system having one or more lens elements. The lens elements may include a plano-convex lens and a plano-concave lens. A partially reflective mirror may be formed on a convex surface of the plano-convex lens. A reflective polarizer may be formed on the planar surface of the plano-convex lens or the concave surface of the plano-concave lens. An additional quarter wave plate may be located between the reflective polarizer and the partially reflective mirror.
    Type: Application
    Filed: January 30, 2020
    Publication date: May 28, 2020
    Inventors: Sajjad A. Khan, Nan Zhu, Graham B. Myhre, Brent J. Bollman, Tyler Anderson, Weibo Cheng, John N. Border
  • Publication number: 20200161175
    Abstract: Back end of line metallization structures and processes of fabricating the metallization structures generally include a top via integration scheme. The top via integration scheme integrally forms the via on top of trench. Thus, the via is fully aligned and can be of a desired critical dimension.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 21, 2020
    Inventors: Chih-Chao Yang, Lawrence A. Clevenger, Benjamin D. Briggs, Brent Anderson
  • Publication number: 20200161451
    Abstract: A semiconductor device and a method for fabricating the same. The semiconductor device includes at least a n-type vertical FET and a p-type vertical FET. The n-type vertical FET includes at least a first bottom source/drain layer. The p-type vertical FET includes at least a second bottom source/drain layer. A silicon dioxide layer separates the first bottom source/drain layer and the second bottom source/drain layer. The method includes forming a first bottom source/drain layer in a p-type vertical FET device area. A germanium dioxide layer is formed in contact with the first semiconductor layer a second semiconductor fin formed within a n-type vertical FET device area. A silicon dioxide layer is formed in contact with the first bottom source/drain layer from the germanium dioxide layer. A second bottom source/drain layer is formed in contact with the second semiconductor fin and the silicon dioxide layer.
    Type: Application
    Filed: November 15, 2018
    Publication date: May 21, 2020
    Inventors: Choonghyun LEE, Ruqiang BAO, SHOGO MOCHIZUKI, Brent A. ANDERSON, Hemanth JAGANNATHAN
  • Publication number: 20200161472
    Abstract: According to an embodiment of the present invention, a semiconductor device includes a plurality of transistors, wherein each of the plurality of transistors includes a first vertical fin connected to a gate and a first doped region, wherein the first doped region is formed on a substrate, a second vertical fin connected to the gate and a source or a drain (S/D), wherein the S/D is formed on the substrate and a bottom contact self-aligned with and connected to the gate and a second doped region. Each of the plurality of transistors is operably connected to form the semiconductor device.
    Type: Application
    Filed: January 21, 2020
    Publication date: May 21, 2020
    Inventors: Brent A. Anderson, Terence B. Hook, Junli Wang
  • Publication number: 20200152619
    Abstract: A method of fabricating a semiconductor device includes forming one or more fins on a substrate. The method includes forming a first active area and a second active area, each including an n-type dopant, on the substrate at opposing ends of the one or more fins. The method further includes forming a third active area including a p-type dopant on the substrate adjacent to the first active area and the second active area.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 14, 2020
    Inventors: Brent A. Anderson, Huiming Bu, Terence B. Hook, Xuefeng Liu, JUNLI WANG