Patents by Inventor Brent Anderson

Brent Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200152619
    Abstract: A method of fabricating a semiconductor device includes forming one or more fins on a substrate. The method includes forming a first active area and a second active area, each including an n-type dopant, on the substrate at opposing ends of the one or more fins. The method further includes forming a third active area including a p-type dopant on the substrate adjacent to the first active area and the second active area.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 14, 2020
    Inventors: Brent A. Anderson, Huiming Bu, Terence B. Hook, Xuefeng Liu, JUNLI WANG
  • Publication number: 20200152791
    Abstract: A method of forming a vertical transport field effect transistor is provided. The method includes forming a vertical fin on a substrate, and a top source/drain on the vertical fin. The method further includes thinning the vertical fin to form a thinned portion, a tapered upper portion, and a tapered lower portion from the vertical fin. The method further includes depositing a gate dielectric layer on the thinned portion, tapered upper portion, and tapered lower portion of the vertical fin, wherein the gate dielectric layer has an angled portion on each of the tapered upper portion and tapered lower portion. The method further includes depositing a work function metal layer on the gate dielectric layer.
    Type: Application
    Filed: January 15, 2020
    Publication date: May 14, 2020
    Inventors: Shogo Mochizuki, Brent A. Anderson, Hemanth Jagannathan, Junli Wang
  • Patent number: 10629443
    Abstract: A method for manufacturing a semiconductor device includes forming a first active region on a semiconductor substrate, forming a semiconductor layer on the first active region, patterning the semiconductor layer into a plurality of fins extending from the first active region vertically with respect to the semiconductor substrate, wherein the first active region is located at bottom ends of the plurality of fins, forming a silicide layer on exposed portions of the first active region, forming an electrically conductive contact on the silicide region, forming a second active region on top ends of each of the plurality of fins, and forming a gate structure between the plurality of fins, wherein the gate structure is positioned over the first active region and under the second active region.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Huiming Bu, Terence B. Hook, Fee Li Lie, Junli Wang
  • Patent number: 10629703
    Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Publication number: 20200118890
    Abstract: Semiconductor devices and methods of forming the same include forming a doped dielectric layer on a semiconductor fin. The doped dielectric layer is annealed to drive dopants from the doped dielectric layer into the semiconductor fin. A gate stack is formed on the semiconductor fin.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 16, 2020
    Inventors: Ruqiang Bao, Junli Wang, Brent A. Anderson, Xin Miao
  • Patent number: 10617061
    Abstract: A compost turning apparatus may include a towable mobile base being elongated in a longitudinal direction and having a lateral direction. The mobile base may comprise a frame, a tongue mounted on the frame, one or more transport wheels mountable in a transport setup and an operational setup, one or more support wheels mounted on the frame, and a drive wheel mounted on the frame. The apparatus may also include a rotor mounted on the mobile base to rotate about an axis oriented substantially parallel to the longitudinal direction of the mobile base. The rotor may have a plurality of paddles arranged in circumferential rows, with various paddle positions and paddle orientations.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: April 14, 2020
    Assignee: Kooima Ag, Inc.
    Inventors: Thor Anderson, Kelly R. Konz, Joel A. Negus, Greg Dejager, Nolan Den Boer, Brent Maassen
  • Patent number: 10622458
    Abstract: Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Steven Bentley, Su Chen Fan, Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
  • Patent number: 10622459
    Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Bruce B. Doris, Seong-Dong Kim, Rajasekhar Venigalla
  • Patent number: 10622477
    Abstract: A vertical transport fin field effect transistor (VTFET) with a smaller cross-sectional area at the top of the fin than at the bottom, including, a substrate, a vertical fin on the substrate, wherein the vertical fin has a cross-sectional area at the base of the vertical fin that is larger than a cross-sectional area at the top of the vertical fin, wherein the cross-sectional area at the top of the vertical fin is in the range of about 10% to about 75% of the cross-sectional area at the base of the vertical fin, and a central gated region between the base and the top of the vertical fin.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10615082
    Abstract: Forming a PFET work function metal layer on a p-type field effect transistor (PFET) fin in a PFET region and on an n-type field effect transistor (NFET) fin in an NFET region, removing a portion of the PFET work function metal layer between the PFET fin and the NFET fin, thinning the PFET work function metal layer, patterning an organic planarization layer on the PFET work function metal layer, where the organic planarization layer covers the PFET region and partially covers the NFET region, removing the PFET work function metal layer in the NFET region, by etching isotropically selective to the organic planarization layer and an insulator in the NFET region, removing the organic planarization layer, and conformally forming an NFET work function metal layer on the semiconductor structure.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Ruqiang Bao, Kangguo Cheng, Hemanth Jagannathan, Choonghyun Lee, Junli Wang
  • Patent number: 10615276
    Abstract: A vertical field-effect transistor (FET) device and an input/output (IO) FET device are formed. The vertical FET device is formed in a vertical FET device area of a substrate and the IO FET device is formed in an IO FET device area of the substrate. Forming the vertical FET device and the IO FET device includes forming a plurality of first fin structures in the vertical FET device area and forming at least two second fin structures in the IO FET device area. The at least two second fin structures are separated by a distance associated with a length of a channel connecting the at least two fin structures in the IO FET device area. The length of the channel is determined based on at least one voltage for implementing the IO FET device.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Xuefeng Liu, Junli Wang, Brent A. Anderson, Terence B. Hook, Gauri Karve
  • Publication number: 20200105769
    Abstract: According to an embodiment of the present invention a semiconductor device includes a plurality of transistors, wherein each of the plurality of transistors includes a vertical fin. The vertical fin includes a bottom source or drain (S/D) and a top (S/D) each formed in a doped region. The fin also includes a gate wrapping around a channel region. A bottom contact is connected to the gate, the first doped region and a second doped region. Each of the plurality of transistors is operably connected to form the semiconductor device.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 2, 2020
    Inventors: Brent A. Anderson, Terence B. Hook, Junli Wang
  • Patent number: 10593797
    Abstract: A method of forming a vertical transport field effect transistor is provided. The method includes forming a vertical fin on a substrate, and a top source/drain on the vertical fin. The method further includes thinning the vertical fin to form a thinned portion, a tapered upper portion, and a tapered lower portion from the vertical fin. The method further includes depositing a gate dielectric layer on the thinned portion, tapered upper portion, and tapered lower portion of the vertical fin, wherein the gate dielectric layer has an angled portion on each of the tapered upper portion and tapered lower portion. The method further includes depositing a work function metal layer on the gate dielectric layer.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shogo Mochizuki, Brent A. Anderson, Hemanth Jagannathan, Junli Wang
  • Patent number: 10591707
    Abstract: A head-mounted display may include a display system and an optical system in a housing. The display system may have a pixel array that produces light associated with images. The display system may also have a linear polarizer through which light from the pixel array passes and a quarter wave plate through which the light passes after passing through the quarter wave plate. The optical system may be a catadioptric optical system having one or more lens elements. The lens elements may include a plano-convex lens and a plano-concave lens. A partially reflective mirror may be formed on a convex surface of the plano-convex lens. A reflective polarizer may be formed on the planar surface of the plano-convex lens or the concave surface of the plano-concave lens. An additional quarter wave plate may be located between the reflective polarizer and the partially reflective mirror.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: March 17, 2020
    Assignee: Apple Inc.
    Inventors: Sajjad A. Khan, Nan Zhu, Graham B. Myhre, Brent J. Bollman, Tyler Anderson, Weibo Cheng, John N. Border
  • Patent number: 10593803
    Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off layer on one or more vertical fin segments, wherein the pinch-off layer has a thickness on the sidewalls of the one or more vertical fin segments, forming a trench mask layer on predetermined portions of the pinch-off layer, removing portions of the pinch-off layer not covered by the trench mask layer, where the removed portions of the pinch-off layer exposes underlying portions of the substrate, and removing at least a portion of the substrate to form one or more isolation region trenches, where the distance of the sidewall of one of the one or more isolation region trenches to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Fee Li Lie, Junli Wang
  • Publication number: 20200075425
    Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 5, 2020
    Inventors: Brent A. ANDERSON, Edward J. NOWAK
  • Publication number: 20200075424
    Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.
    Type: Application
    Filed: November 11, 2019
    Publication date: March 5, 2020
    Inventors: Brent A. ANDERSON, Edward J. NOWAK
  • Publication number: 20200066903
    Abstract: A semiconductor structure includes a substrate, a bottom source/drain region disposed on a top surface of the substrate, and a plurality of fins disposed over a top surface of the bottom source/drain region. The fins provide vertical transport channels for one or more vertical transport field-effect transistors. The semiconductor structure also includes at least one self-aligned shared contact disposed between an adjacent pair of the plurality of fins. The adjacent pair of the plurality of fins includes a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Inventors: Ruqiang Bao, Brent A. Anderson, ChoongHyun Lee, Hemanth Jagannathan
  • Publication number: 20200066906
    Abstract: A method for fabricating a semiconductor device includes forming a vertical field-effect transistor (FET) device including a plurality of first fin structures in a vertical FET device area of a substrate, and forming an input/output (IO) FET device including at least two second fin structures in an IO FET device area of the substrate. The at least two fin structures are connected by a channel having a length determined based on at least one voltage for implementing the IO FET device. Forming the vertical FET and IO FET devices includes selectively exposing a portion of the IO FET device area by selectively removing a portion of a first spacer formed on the substrate in the IO FET device area.
    Type: Application
    Filed: October 31, 2019
    Publication date: February 27, 2020
    Inventors: Xuefeng Liu, Junli Wang, Brent A. Anderson, Terence B. Hook, Gauri Karve
  • Patent number: D883920
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: May 12, 2020
    Assignee: Brightz, ltd.
    Inventor: Brent Anderson