Patents by Inventor Brent Anderson

Brent Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200066603
    Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a bottom source/drain region disposed over a top surface of a substrate, the fins providing vertical transport channels for a plurality of vertical transport field-effect transistors. The method also includes forming a first gate conductor surrounding a first one of an adjacent pair of the plurality of fins providing a first vertical transport channel for a first vertical transport field-effect transistor, forming a second gate conductor surrounding a second one of the adjacent pair of the plurality of fins providing a second vertical transport channel for a second vertical transport field-effect transistor, and forming at least one shared gate contact to the first gate conductor and the second gate conductor, the at least one shared gate contact being formed at first ends of the adjacent pair of the plurality of fins.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Brent A. Anderson, ChoongHyun Lee
  • Publication number: 20200066711
    Abstract: Embodiments of the invention include first and second devices formed on a substrate. The first device includes a bottom source or drain (S/D) region, a plurality of fins formed on portions of the bottom S/D region, a bottom spacer formed on the bottom S/D region, a dielectric layer, a gate, a top S/D region formed on each fin of a plurality of fins, and one or more contacts. The dielectric layer is disposed between the gate and the fin of the plurality of fins. The second device includes a bottom doped region, a channel formed the bottom doped region, a sidewall doped region of the channel, a gate coupled to the sidewall doped region, a top doped region, and one or more contacts. A junction is formed between the channel and the sidewall doped region. The cap layer is formed on the gate and the top doped region.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 27, 2020
    Inventors: Brent A. Anderson, Huiming Bu, Terence B. Hook, Xuefeng Liu, Junli Wang
  • Patent number: 10573562
    Abstract: One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10573727
    Abstract: According to an embodiment of the present invention, a method for forming a semiconductor device includes pattering a first fin in a semiconductor substrate, and forming a liner layer over the first fin. The method further includes removing a first portion of the liner layer, and removing a portion of the exposed semiconductor substrate to form a first cavity. The method also includes performing an isotropic etching process to remove portions of the semiconductor substrate in the first cavity and form a first undercut region below the liner layer, growing a first epitaxial semiconductor material in the first undercut region and the first cavity, and performing a first annealing process to drive dopants from the first epitaxial semiconductor material into the first fin to form a first source/drain layer under the first fin and in portions of the semiconductor substrate.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Huiming Bu, Fee Li Lie, Shogo Mochizuki, Junli Wang
  • Publication number: 20200057091
    Abstract: An aircraft probe includes a base, a strut that extends from the base, at least one port, and an electronics assembly insertable into the strut and removable from the strut. The electronics assembly includes at least one pressure sensor that is pneumatically connected to the at least one port to sense a first pressure when in the inserted position.
    Type: Application
    Filed: August 17, 2018
    Publication date: February 20, 2020
    Inventors: Brian Brent Naslund, Matthew Paul Anderson, Benjamin John Langemo, Andrew Sherman
  • Patent number: 10566453
    Abstract: According to an embodiment of the present invention, a method for forming a contact for a transistor includes forming a first doped region over a semiconductor substrate. A first fin is formed over the first doped region. A gate is formed alongside portions of the first fin. A void is created by removing the first fin to expose a portion of the first doped region. A metal is deposited in the void to create the contact.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Terence B. Hook, Junli Wang
  • Publication number: 20200052096
    Abstract: Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having self-aligned contacts. In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source/drain region of a substrate. A conductive gate is formed over a channel region of the semiconductor fin. A top source/drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source/drain region. A dielectric cap is formed over the top metallization layer.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: Brent A. Anderson, Steven Bentley, Su Chen Fan, Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
  • Publication number: 20200052079
    Abstract: A method of forming a semiconductor structure includes forming at least one fin disposed over a top surface of a substrate, the fin providing a vertical transport channel for a vertical transport field-effect transistor. The method also includes forming a top source/drain region disposed over a top surface of the fin, and forming a first contact trench at a first end of the fin and a second contact trench at a second end of the fin, the first and second contact trenches being self-aligned to the top source/drain region. The method further includes forming inner spacers on sidewalls of the first contact trench and the second contact trench, and forming contact material in the first contact trench and the second contact trench between the inner spacers. The contact material comprises a stressor material that induces vertical strain in the fin.
    Type: Application
    Filed: August 13, 2018
    Publication date: February 13, 2020
    Inventors: Juntao Li, Kangguo Cheng, Brent A. Anderson
  • Patent number: 10559572
    Abstract: According to an embodiment of the present invention, a method for forming a contact for a transistor includes forming a first doped region over a semiconductor substrate. A second doped region is formed in portions of the first doped region in which portions the first doped region extends below the second doped region. A gate is formed alongside portions of a first fin. Portions of the second doped region and portions of the first doped region extending below the second doped region are removed. Portions of the gate are removed. A metal is deposited in the removed portion of the gate, the removed portion of second doped region, and the first doped region extending below the second doped region to create the contact.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Terence B. Hook, Junli Wang
  • Publication number: 20200028513
    Abstract: A semiconductor structure includes a vertical transport logic circuit cell. The vertical transport logic cell includes a first logic gate and at least a second logic gate. The first logic gate includes at least one input terminal and at least one output terminal. The second logic gate includes at least one input terminal and at least one output terminal. One of the input terminal and the output terminal of the first logic gate shares a pitch of the vertical transport logic circuit cell with one of the input terminal and the output terminal of the second logic gate. The first and second logic gates can include the same type or different types of logic functions.
    Type: Application
    Filed: July 23, 2018
    Publication date: January 23, 2020
    Inventors: Brent A. Anderson, Albert Chu
  • Publication number: 20200020591
    Abstract: A method for forming a semiconductor device includes flipping a vertical transistor including a bottom side having at least one connection to at least one bottom side metallization structure, and, after flipping the vertical transistor, forming at least one top side metallization structure having at least one connection to a top side of the vertical transistor.
    Type: Application
    Filed: September 24, 2019
    Publication date: January 16, 2020
    Inventors: Brent A. Anderson, Albert M. Chu
  • Publication number: 20200019665
    Abstract: A computer-implemented method of cell placement is provided. The method includes representing a non-rectangular cell to be placed into a cell row and searching the cell row to identify existing objects that are representative of cells in the cell row that are disposable to share space with the non-rectangular cell. The method further includes determining whether a representation of the non-rectangular cell is fittable into a modified mapping of the existing objects in the cell row and, in an event the representation is fittable into the modified mapping, overlapping the representation over one or more of the portions of the existing objects.
    Type: Application
    Filed: July 12, 2018
    Publication date: January 16, 2020
    Inventors: BRENT A. ANDERSON, LAURA R. DARDEN, ALBERT M. CHU, ALEXANDER J. SUESS
  • Publication number: 20200013891
    Abstract: A semiconductor device includes a substrate having an input/output (IO) field-effect transistor (FET) device area, and an IO FET device formed in the IO FET device area. The IO FET device includes at least two fin structures separated by a distance associated with a length of a channel connecting the at least two fin structures. The length of the channel is determined based on at least one voltage for implementing the IO FET device.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Inventors: Xuefeng Liu, Junli Wang, Brent A. Anderson, Terence B. Hook, Gauri Karve
  • Patent number: 10529625
    Abstract: A method for forming a semiconductor device includes forming bottom side metallization structures having at least one connection to a bottom side of a vertical transistor disposed on a substrate, the bottom side metallization structures including a power rail and a ground rail. After forming the bottom side metallization structures, the substrate is removed and the vertical transistor is flipped. Top side metallization structures are formed. The top side metallization structures having at least one connection to the vertical transistor on a top side of the vertical transistor.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Albert M. Chu
  • Patent number: 10529627
    Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Publication number: 20200006353
    Abstract: According to an embodiment of the present invention, a method for forming a contact for a transistor includes forming a first doped region over a semiconductor substrate. A second doped region is formed in portions of the first doped region in which portions the first doped region extends below the second doped region. A gate is formed alongside portions of a first fin. Portions of the second doped region and portions of the first doped region extending below the second doped region are removed. Portions of the gate are removed. A metal is deposited in the removed portion of the gate, the removed portion of second doped region, and the first doped region extending below the second doped region to create the contact.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Brent A. Anderson, Terence B. Hook, Junli Wang
  • Publication number: 20200006552
    Abstract: According to an embodiment of the present invention, a method for forming a contact for a transistor includes forming a first doped region over a semiconductor substrate. A first fin is formed over the first doped region. A gate is formed alongside portions of the first fin. A void is created by removing the first fin to expose a portion of the first doped region. A metal is deposited in the void to create the contact.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Brent A. Anderson, Terence B. Hook, Junli Wang
  • Publication number: 20190393341
    Abstract: A method of forming a vertical transport field effect transistor is provided. The method includes forming a vertical fin on a substrate, and a top source/drain on the vertical fin. The method further includes thinning the vertical fin to form a thinned portion, a tapered upper portion, and a tapered lower portion from the vertical fin. The method further includes depositing a gate dielectric layer on the thinned portion, tapered upper portion, and tapered lower portion of the vertical fin, wherein the gate dielectric layer has an angled portion on each of the tapered upper portion and tapered lower portion. The method further includes depositing a work function metal layer on the gate dielectric layer.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 26, 2019
    Inventors: Shogo Mochizuki, Brent A. Anderson, Hemanth Jagannathan, Junli Wang
  • Publication number: 20190383850
    Abstract: A system includes a probe, a transducer, and a sealing feature. The probe is detachable and includes a first gas path extending from a head to a mount. The transducer is configured to mate with the mount and includes a second gas path with an inlet configured to be in fluid communication with the outlet of the first gas path when the transducer is mated with the mount and at least one sensor disposed along the second gas path. The sealing feature includes a first membrane configured to allow pressure to be conveyed from the first gas path to the second gas path when the transducer is mated with the mount while preventing contaminants from entering the second gas path when the transducer is distant from the probe.
    Type: Application
    Filed: October 10, 2018
    Publication date: December 19, 2019
    Inventors: Brian Brent Naslund, Benjamin John Langemo, Matthew Paul Anderson, Andrew Sherman
  • Publication number: 20190383849
    Abstract: A system includes a probe and a transducer. The probe is detachable and includes a mount having an outlet of a first gas path extending through the probe and a protrusion extending away from the mount. The transducer is configured to mate with the mount and includes a sealing feature adjacent an inlet of the second gas path in fluid communication with the first gas path. When the mount of the probe is adjacent the transducer, the protrusion interacts with the sealing feature such that the sealing feature is in an open position to allow air to flow from the first gas path into the second gas path. When the mount of the probe is distant from the transducer, the sealing feature is in a closed position to prevent contaminants from entering the second gas path.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Inventors: Brian Brent Naslund, Benjamin John Langemo, Matthew Paul Anderson, Andrew Sherman