Abstract: A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits.

Abstract: An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and second power rails adapted for connection to a voltage supply and a voltage return, respectively, of the standard cells. Each standard cell in a subset of the standard cells is arranged in direct abutment with at least two other standard cells, and at least first and second end cells are arranged in direct abutment with at least one other standard cell of the first plurality of standard cells. The power mesh power connection structure includes a plurality of conductive elements formed in a plurality of different conductive layers in the integrated circuit.

Abstract: An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and second power rails adapted for connection to a voltage supply and a voltage return, respectively, of the standard cells. Each standard cell in a subset of the standard cells is arranged in direct abutment with at least two other standard cells, and at least first and second end cells are arranged in direct abutment with at least one other standard cell of the first plurality of standard cells. The power mesh power connection structure includes a plurality of conductive elements formed in a plurality of different conductive layers in the integrated circuit.

Abstract: A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits.

Abstract: An automated framework and methodology for the development, testing, validation, and documentation of the design of semiconductor products that culminates in the release of a design kit having a flow manager and flow file to actualize a methodology to design a semiconductor product. The flow framework and methodology receives a methodology and a technology description for the semiconductor product. Then the flow framework and methodology coordinates and tests flow files developed by flow developers using testcases from testcase developers, libraries from library developers and tools from tool from flow developers that may be constantly updated. When a flow file, a testcase, a library, and/or a tool is updated, added, or otherwise changed, ongoing regression testing is accomplished to update the correct flow file.

Abstract: A pre-diffused high density array of core memory cells is provided in a metal programmable device. The peripheral logic is made up of gate array cells in the metal programmable device. The peripheral logic may be configured to access the core memory cells as various memory types, widths, depths, and other configurations. If the entire memory is not needed, then the unused memory cells can be used as logic gates. The application-specific circuit, including peripheral logic, memory interface logic, and memory configuration is programmed with a metal layer.

Abstract: A pre-diffused high density array of core memory cells is provided in a metal programmable device. The peripheral logic is made up of gate array cells in the metal programmable device. The peripheral logic may be configured to access the core memory cells as various memory types, widths, depths, and other configurations. If the entire memory is not needed, then the unused memory cells can be used as logic gates. The application-specific circuit, including peripheral logic, memory interface logic, and memory configuration is programmed with a metal layer.

Abstract: An automated framework and methodology for the development, testing, validation, and documentation of the design of semiconductor products that culminates in the release of a design kit having a flow manager and flow file to actualize a methodology to design a semiconductor product. The flow framework and methodology receives a methodology and a technology description for the semiconductor product. Then the flow framework and methodology coordinates and tests flow files developed by flow developers using testcases from testcase developers, libraries from library developers and tools from tool from flow developers that may be constantly updated. When a flow file, a testcase, a library, and/or a tool is updated, added, or otherwise changed, ongoing regression testing is accomplished to update the correct flow file.