Patents by Inventor Bret Ronald Olszewski

Bret Ronald Olszewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10776143
    Abstract: A technique for assigning physical resources of a data processing system to a virtual machine (VM) includes reading, by a hypervisor executing on the data processing system, a fold factor attribute for the VM. The fold factor attribute defines an anticipated usage of physical resources of the data processing system by the VM. The technique also includes mapping based on a value of the fold factor attribute, by the hypervisor, allocated virtual processors of the VM to the physical resources to maximize processor core access to local memory for ones of the allocated virtual processors that are anticipated to be utilized.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peter Joseph Heyrman, Bret Ronald Olszewski, Sergio Reyes
  • Patent number: 10740127
    Abstract: A technique for assigning physical resources of a data processing system to a virtual machine (VM) includes reading, by a hypervisor executing on the data processing system, a fold factor attribute for the VM. The fold factor attribute defines an anticipated usage of physical resources of the data processing system by the VM. The technique also includes mapping based on a value of the fold factor attribute, by the hypervisor, allocated virtual processors of the VM to the physical resources to maximize processor core access to local memory for ones of the allocated virtual processors that are anticipated to be utilized.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peter Joseph Heyrman, Bret Ronald Olszewski, Sergio Reyes
  • Patent number: 9354934
    Abstract: Interrupt-intensive and interrupt-driven processes are managed among a plurality of virtual processors, wherein each virtual processor is associated with a physical processor, wherein each physical processor may be associated with a plurality of virtual processors, and wherein each virtual processor is tasked to execute one or more of the processes, by determining which of a plurality of the processes executing among a plurality of virtual processors are being or have been driven by at least a minimum count of interrupts over a period of operational time; selecting a subset of the plurality of virtual processors to form a sequestration pool; migrating the interrupt-intensive processes on to the sequestration pool of virtual processors; and commanding by a computer a bias in delivery or routing of the interrupts to the sequestration pool of virtual processors.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: May 31, 2016
    Assignee: International Business Machines Corporation
    Inventors: Mathew Accapadi, Grover Cleveland Davidson, II, Dirk Michel, Bret Ronald Olszewski
  • Publication number: 20150363218
    Abstract: A technique for assigning physical resources of a data processing system to a virtual machine (VM) includes reading, by a hypervisor executing on the data processing system, a fold factor attribute for the VM. The fold factor attribute defines an anticipated usage of physical resources of the data processing system by the VM. The technique also includes mapping based on a value of the fold factor attribute, by the hypervisor, allocated virtual processors of the VM to the physical resources to maximize processor core access to local memory for ones of the allocated virtual processors that are anticipated to be utilized.
    Type: Application
    Filed: September 19, 2014
    Publication date: December 17, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: PETER JOSEPH HEYRMAN, BRET RONALD OLSZEWSKI, SERGIO REYES
  • Publication number: 20150363217
    Abstract: A technique for assigning physical resources of a data processing system to a virtual machine (VM) includes reading, by a hypervisor executing on the data processing system, a fold factor attribute for the VM. The fold factor attribute defines an anticipated usage of physical resources of the data processing system by the VM. The technique also includes mapping based on a value of the fold factor attribute, by the hypervisor, allocated virtual processors of the VM to the physical resources to maximize processor core access to local memory for ones of the allocated virtual processors that are anticipated to be utilized.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 17, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: PETER JOSEPH HEYRMAN, BRET RONALD OLSZEWSKI, SERGIO REYES
  • Patent number: 8850402
    Abstract: Methods, systems, and products for determining performance of a software entity running on a data processing system. The method comprises allowing extended execution of the software entity without monitoring code. The method also comprises intermittently sampling behavior data for the software entity. Intermittently sampling behavior data may be carried out by injecting monitoring code into the software entity to instrument the software entity, collecting behavior data by utilizing the monitoring code, and removing the monitoring code. The method also comprises repeatedly performing iterations of the allowing and sampling steps until collected behavior data is sufficient for diagnosing performance of the software entity. The method may further comprise analyzing the collected behavior data to diagnose performance of the software entity.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Randall Ray Heisch, Bret Ronald Olszewski
  • Patent number: 8689222
    Abstract: A method, a system and a computer program product for controlling the hardware priority of hardware threads in a data processing system. A Thread Priority Control (TPC) utility assigns a primary level and one or more secondary levels of hardware priority to a hardware thread. When a hardware thread initiates execution in the absence of a system call, the TPC utility enables execution based on the primary level. When the hardware thread initiates execution within a system call, the TPC utility dynamically adjusts execution from the primary level to the secondary level associated with the system call. The TPC utility adjusts hardware priority levels in order to: (a) raise the hardware priority of one hardware thread relative to another; (b) reduce energy consumed by the hardware thread; and (c) fulfill requirements of time critical hardware sections.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: April 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Vaijayanthimala K. Anand, Joerg Droste, Bruce Mealey, Bret Ronald Olszewski
  • Patent number: 8589926
    Abstract: A method, system, and computer usable program product for adjusting processor utilization data in polling environments are provided in the illustrative embodiments. An amount of a computing resource consumed during polling performed by the polling application over a predetermined period is received at a processor in a data processing system from a polling application executing in the data processing system. The amount forms a polling amount of the computing resource. Using the polling amount of the computing resource, another amount of the computing resource consumed for performing meaningful task is determined. The other amount forms a work amount of the computing resource. Using the work amount of the computing resource, an adjusted utilization of the computing resource is computed over a utilization interval. The data of the adjusted utilization is saved.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jimmy Ray Hill, Bret Ronald Olszewski, Luc Rene Smolders, David Blair Whitworth
  • Patent number: 8489824
    Abstract: A method, system, and computer usable program product for selective memory compression for multi-threaded applications are provided in the illustrative embodiments. An identification of a memory region that is shared by a plurality of threads in an application is received at a first entity in a data processing system. A request for a second entity in the data processing system to keep the memory region uncompressed when compressing at least one of a plurality of memory regions that comprise the memory region is provided from the first entity to the second entity.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mathew Accapadi, Grover Cleveland Davidson, II, Dirk Michel, Bret Ronald Olszewski
  • Publication number: 20130179616
    Abstract: Interrupt-intensive and interrupt-driven processes are managed among a plurality of virtual processors, wherein each virtual processor is associated with a physical processor, wherein each physical processor may be associated with a plurality of virtual processors, and wherein each virtual processor is tasked to execute one or more of the processes, by determining which of a plurality of the processes executing among a plurality of virtual processors are being or have been driven by at least a minimum count of interrupts over a period of operational time; selecting a subset of the plurality of virtual processors to form a sequestration pool; migrating the interrupt-intensive processes on to the sequestration pool of virtual processors; and commanding by a computer a bias in delivery or routing of the interrupts to the sequestration pool of virtual processors.
    Type: Application
    Filed: January 5, 2012
    Publication date: July 11, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mathew Accapadi, Grover Cleveland Davidson, II, Dirk Michel, Bret Ronald Olszewski
  • Patent number: 8468289
    Abstract: A method of dynamically reallocating memory affinity in a virtual machine after migrating the virtual machine from a source computer system to a destination computer system migrates processor states and resources used by the virtual machine from the source computer system to the destination computer system. The method maps memory of the virtual machine to processor nodes of the destination computer system. The method deletes memory mappings in processor hardware, such as translation lookaside buffers and effective-to-real address tables, for the virtual machine on the destination computer system. The method starts the virtual machine on the destination computer system in virtual real memory mode. A hypervisor running on the destination computer system receives a page fault and virtual address of a page for said virtual machine from a processor of the destination computer system and determines if the page is in local memory of the processor.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: June 18, 2013
    Assignee: International Business Machines Corporation
    Inventors: David Alan Hepkin, Peter Joseph Heyrman, Bret Ronald Olszewski
  • Patent number: 8458401
    Abstract: Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein the shared cache memory is effectively shared on a line-by-line basis among the plurality of logical processing partitions of the multi-core processor.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bret Ronald Olszewski, Steven Wayne White
  • Patent number: 8447929
    Abstract: Associativity of a multi-core processor cache memory to a logical partition is managed and controlled by receiving a plurality of unique logical processing partition identifiers into registration of a multi-core processor, each identifier being associated with a logical processing partition on one or more cores of the multi-core processor; responsive to a shared cache memory miss, identifying a position in a cache directory for data associated with the address, the shared cache memory being multi-way set associative; associating a new cache line entry with the data and one of the registered unique logical processing partition identifiers; modifying the cache directory to reflect the association; and caching the data at the new cache line entry, wherein said shared cache memory is effectively shared on a line-by-line basis among said plurality of logical processing partitions of said multi-core processor.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Bret Ronald Olszewski, Steven Wayne White
  • Patent number: 8359449
    Abstract: A method manages memory paging operations. Responsive to a request to page out a memory page from a shared memory pool, the method identifies whether a physical space within one of a number of paging space devices has been allocated for the memory page. If physical space within the paging space device has not been allocated for the memory page, a page priority indicator for the memory page is identified. The memory page is then allocated to one of a number of memory pools within one of the number of paging space devices. The memory page is allocated one of the memory pools according to the page priority indicator of the memory page. The memory page is then written to the allocated memory pools.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: January 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mathew Accapadi, Dirk Michel, Bret Ronald Olszewski
  • Patent number: 8327176
    Abstract: Distributing a thread for running on a physical processor and enabling the physical processor to be switched into a low power snooze state when said running thread is IDLE. However, this switching into said low power state is enabled to be delayed by a delay time from an IDLE dispatch from said running thread; such delay is determined by tracking the rate of the number of said IDLE dispatches per processor clock interval and dynamically varying said delay time wherein the delay time is decreased when said rate of IDLE dispatches increases and the delay time is increased when said rate of IDLE dispatches decreases.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: December 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Mathew Accapadi, Grover Cleveland Davidson, II, Dirk Michel, Bret Ronald Olszewski
  • Publication number: 20120297216
    Abstract: Dynamically selecting active polling or timed waits by a server in a clustered system includes determining a load ratio of a processor of the server, which is determined by calculating a ratio of an instantaneous run queue occupancy to a number of cores of the processor. The processor is occupied by a first runnable thread that requires a message response. A determination may be made whether power management is enabled on the processor, an instantaneous state may be determined based on the load ratio and whether power management is enabled on the processor, and a state process corresponding to the instantaneous state may be executed.
    Type: Application
    Filed: May 19, 2011
    Publication date: November 22, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bret Ronald Olszewski, Kelvin Ho, Roy Robert Cecil
  • Patent number: 8312456
    Abstract: An approach is provided that retrieves a time spent value corresponding to a selected partition that is selected from a group of partitions included in a virtualized environment running on a computer system. The virtualized environment is provided by a Hypervisor. The time spent value corresponds to an amount of time the selected partition has spent processing interrupts. A number of virtual CPUs have been assigned to the selected partition. The time spent value (e.g., a percentage of the time that the selected partition spends processing interrupts) is compared to one or more interrupt threshold values. If the comparison reveals that the time that the partition is spending processing interrupts exceeds a threshold, then the number of virtual CPUs assigned to the selected partition is increased.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: November 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: David Alan Hepkin, Sujatha Kashyap, Bret Ronald Olszewski
  • Patent number: 8307188
    Abstract: An information handling system (IHS) loads an application that may include startup code and steady state operation code. The IHS allocates one region of system memory to the startup code and another region of system memory to the steady state operation code. A programmer inserts a memory release call command at a location that marks the end of execution of the startup code. After executing the startup code, the operation system receives the memory release call command. In response to the memory release call command, the operating system releases or de-allocates the region of memory to which the IHS previously assigned to the startup code. This enables the released memory for use by code other than the startup code, such as other code pages, library pages and other code.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: November 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Mathew Accapadi, Grover Cleveland Davidson, II, Dirk Michel, Bret Ronald Olszewski
  • Publication number: 20120210331
    Abstract: An operating system or virtual machine of an information handling system (IHS) initializes a resource manager to provide processor resource utilization management during workload or application execution. The resource manager captures short term interval (STI) and long term interval (LTI) processor resource utilization data and stores that utilization data within an information store of the virtual machine. If a capacity on demand mechanism is enabled, the resource manager modifies a reserved capacity value. The resource manager selects previous STI and LTI values for comparison with current resource utilization and may apply a safety margin to generate a reserved capacity or target resource utilization value for the next short term interval (STI). The hypervisor may modify existing virtual processor allocation to match the target resource utilization.
    Type: Application
    Filed: April 21, 2012
    Publication date: August 16, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Grover Cleveland Davidson, II, Dirk Michel, Bret Ronald Olszewski, Marcos A. Villarreal
  • Publication number: 20120204186
    Abstract: An operating system or virtual machine of an information handling system (IHS) initializes a resource manager to provide processor resource utilization management during workload or application execution. The resource manager captures short term interval (STI) and long term interval (LTI) processor resource utilization data and stores that utilization data within an information store of the virtual machine. If a capacity on demand mechanism is enabled, the resource manager modifies a reserved capacity value. The resource manager selects previous STI and LTI values for comparison with current resource utilization and may apply a safety margin to generate a reserved capacity or target resource utilization value for the next short term interval (STI). The hypervisor may modify existing virtual processor allocation to match the target resource utilization.
    Type: Application
    Filed: February 9, 2011
    Publication date: August 9, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Grover Cleveland Davidson, II, Dirk Michel, Bret Ronald Olszewski, Marcos A. Villarreal