Patents by Inventor Bret Rothenberg

Bret Rothenberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8942572
    Abstract: A lighting system includes light fixtures not in communications with and not synchronized with one another, and one or more light sensors. Each light fixture separately emits data encoded visible light including light fixture information encoded therein in a manner that avoids visually perceptible flicker and enables light fixture information emitted by one light fixture to be distinguished from light fixture information emitted by other light fixtures. The light fixture information is encoded into data encoded visible light such that a difference between different levels of the data encoded visible light is indicative of an illumination capability of the light fixture and such that visually perceptible flicker is avoided. Each light sensor separately receives portions of data encoded light visible light emitted by multiple light fixtures and separately determines the identity of and the maximum and present illumination contributions for each light fixture.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: January 27, 2015
    Inventor: Bret Rothenberg
  • Publication number: 20140270794
    Abstract: A lighting system includes light fixtures not in communications with and not synchronized with one another, and one or more light sensors. Each light fixture separately emits data encoded visible light including light fixture information encoded therein in a manner that avoids visually perceptible flicker and enables light fixture information emitted by one light fixture to be distinguished from light fixture information emitted by other light fixtures. The light fixture information is encoded into data encoded visible light such that a difference between different levels of the data encoded visible light is indicative of an illumination capability of the light fixture and such that visually perceptible flicker is avoided. Each light sensor separately receives portions of data encoded light visible light emitted by multiple light fixtures and separately determines the identity of and the maximum and present illumination contributions for each light fixture.
    Type: Application
    Filed: February 21, 2014
    Publication date: September 18, 2014
    Inventor: Bret Rothenberg
  • Patent number: 8699887
    Abstract: A lighting system includes light fixtures not in communications with and not synchronized with one another, and one or more light sensors. Each light fixture separately emits data encoded visible light including light fixture information encoded therein in a manner that avoids visually perceptible flicker and enables light fixture information emitted by one light fixture to be distinguished from light fixture information emitted by other light fixtures. The light fixture information is encoded into data encoded visible light such that a difference between different levels of the data encoded visible light is indicative of an illumination capability of the light fixture and such that visually perceptible flicker is avoided. Each light sensor separately receives portions of data encoded light visible light emitted by multiple light fixtures and separately determines the identity of and the maximum and present illumination contributions for each light fixture.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 15, 2014
    Inventor: Bret Rothenberg
  • Patent number: 8648583
    Abstract: Embodiments for at least one method and apparatus for controlling timing of switch control signals of a switching voltage regulator disclosed. One method includes generating a regulated output voltage based upon a switching voltage, generating the switching voltage through controlled closing and opening of a series switch element and a shunt switch element, and controlling, by a delay block, the closing and opening of the series switch element and a shunt switch element. The delay block control includes receiving, by the delay block, a timing signal, generating a one of a series switch control signal and a shunt switch control signal by controllably delaying the timing signal with a first delay, and generating one other of the series switch control signal and the shunt switch control signal by inverting, and controllably delaying the timing signal with a second delay.
    Type: Grant
    Filed: September 3, 2011
    Date of Patent: February 11, 2014
    Assignee: R2 Semiconductor, Inc.
    Inventors: James E. C. Brown, Bret Rothenberg
  • Patent number: 8339115
    Abstract: Embodiments for at least one method and apparatus of controlling a bypass resistance of a voltage regulator are disclosed. One method includes generating a regulated output voltage based upon a switching voltage. The switching voltage is generated through controlled closing and opening of a series switch element and a shunt switch element, the series switch element and the shunt switch element being connected between voltages based on an input voltage. Control of a duty cycle of the switching voltage is provided by sensing and feeding back the regulated output voltage. The bypass resistance is controlled based on an integration of a difference between the duty cycle and a maximum duty cycle.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: December 25, 2012
    Assignee: R2 Semiconductor, Inc.
    Inventors: James E. C. Brown, Bret Rothenberg, Lawrence M. Burns
  • Publication number: 20120274297
    Abstract: Embodiments for at least one method and apparatus of controlling a bypass resistance of a voltage regulator are disclosed. One method includes generating a regulated output voltage based upon a switching voltage. The switching voltage is generated through controlled closing and opening of a series switch element and a shunt switch element, the series switch element and the shunt switch element being connected between voltages based on an input voltage. Control of a duty cycle of the switching voltage is provided by sensing and feeding back the regulated output voltage. The bypass resistance is controlled based on an integration of a difference between the duty cycle and a maximum duty cycle.
    Type: Application
    Filed: July 5, 2012
    Publication date: November 1, 2012
    Applicant: R2 SEMICONDUCTOR, INC.
    Inventors: James E.C. Brown, Bret Rothenberg, Lawrence M. Burns
  • Patent number: 8248044
    Abstract: Embodiments for at least one method and apparatus of controlling a bypass resistance of a voltage regulator are disclosed. One method includes generating a regulated output voltage based upon a switching voltage. The switching voltage is generated through controlled closing and opening of a series switch element and a shunt switch element, the series switch element and the shunt switch element being connected between voltages based on an input voltage. A control of a duty cycle of the switching voltage is provided by sensing and feeding back the regulated output voltage. The bypass resistance is controlled based on a parameter related to the duty cycle, wherein the control of the duty cycle is persistent during the control of the bypass resistance.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: August 21, 2012
    Assignee: R2 Semiconductor, Inc.
    Inventors: James E. C. Brown, Bret Rothenberg, Lawrence M. Burns
  • Publication number: 20110234187
    Abstract: Embodiments for at least one method and apparatus of controlling a bypass resistance of a voltage regulator are disclosed. One method includes generating a regulated output voltage based upon a switching voltage. The switching voltage is generated through controlled closing and opening of a series switch element and a shunt switch element, the series switch element and the shunt switch element being connected between voltages based on an input voltage. A control of a duty cycle of the switching voltage is provided by sensing and feeding back the regulated output voltage. The bypass resistance is controlled based on a parameter related to the duty cycle, wherein the control of the duty cycle is persistent during the control of the bypass resistance.
    Type: Application
    Filed: March 24, 2010
    Publication date: September 29, 2011
    Applicant: R2 Semiconductor, Inc.
    Inventors: James E. C. Brown, Bret Rothenberg, Lawrence M. Burns
  • Patent number: 7155179
    Abstract: A full-duplex transceiver using a method immunizing itself against self-jamming. The transceiver includes a receiver and a transmitter. The receiver includes a frequency immunization converter and a high pass IF filter. The transmitter transmits a TX signal. The receiver receives an RX signal and simultaneously receives a portion of the power of the TX signal as an undesired TX jamming signal. The frequency immunization converter uses the center frequency of the TX signal for downconverting the RX signal to an IF signal and simultaneously downconverting the TX jamming signal to near zero frequency. The high pass IF filter passes the IF signal and blocks the signal at near zero frequency. As a consequence of the downconversion using the TX frequency, a second LO frequency is controlled for avoiding image frequencies.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: December 26, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Bret Rothenberg
  • Patent number: 7123665
    Abstract: A method and apparatus for generating a burst FSK signal having precisely shaped transitions between modulation states. The apparatus uses feedforward compensation of phase gain and phase preemphasis coefficients for compensating the frequency conversion gain of the apparatus, and the phase gain coefficient is used for stabilizing a frequency synthesis loop. The phase gain and preemphasis coefficients are determined in a calibration within the time constraints of on-line signal bursts based upon measured phase errors and accelerated predicted phase gain and preemphasis phase errors.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: October 17, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: James E. C. Brown, Bret Rothenberg
  • Patent number: 7123666
    Abstract: A method and apparatus for generating a burst FSK signal having precisely shaped transitions between modulation states. The apparatus uses feedforward compensation of phase gain and phase preemphasis coefficients for compensating the frequency conversion gain of the apparatus, and the phase gain coefficient is used for stabilizing a frequency synthesis loop. The phase gain and preemphasis coefficients are determined in a calibration within the time constraints of on-line signal bursts based upon measured phase errors and accelerated predicted phase gain and preemphasis phase errors.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: October 17, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: James E. C. Brown, Bret Rothenberg, Chienkuo Vincent Tien
  • Patent number: 6950478
    Abstract: An apparatus and a method having a low sampling clock frequency for converting a digital signal having IF frequency channels to an analog IF signal. A DAC uses the sampling signal for converting the digital signal to the analog IF signal. A high-low RFLO signal generator generates an RFLO signal that is controlled to switch between a first RFLO frequency below a desired RF frequency band and a second RFLO frequency above the desired RF frequency band. The RF upconverter uses the first RFLO frequency for upconverting IF frequency channels into RF frequency channels in the lower half of the RF frequency band and uses the second RFLO frequency for upconverting the same IF frequency channels into different RF frequency channels in the upper half of the RF frequency band, thereby enabling the DAC to use a lower frequency sampling signal.
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: September 27, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Bret Rothenberg
  • Patent number: 6940930
    Abstract: A method and apparatus for balancing I/Q gain and I/Q phase in a signal receiver. The receiver includes an IQ coefficient calculator and an IQ balancer. The IQ coefficient calculator computes a set of correction coefficients for each packet from the I and Q signals in an IQ measurement section at the front of the packet. The IQ balancer uses the correction coefficients for correcting the I/Q gain and I/Q phase errors on a packet-by-packet basis. Optionally, delay devices delay the I and Q signals so that the correction coefficients may be applied to the entire packet, or the portion of the packet in the IQ measurement section is passed through uncorrected and the correction coefficients are applied to the packet after the IQ measurement section.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: September 6, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: James E. C. Brown, Bret Rothenberg
  • Publication number: 20040223558
    Abstract: A method and apparatus for generating a burst FSK signal having precisely shaped transitions between modulation states. The apparatus uses feedforward compensation of phase gain and phase preemphasis coefficients for compensating the frequency conversion gain of the apparatus, and the phase gain coefficient is used for stabilizing a frequency synthesis loop. The phase gain and preemphasis coefficients are determined in a calibration within the time constraints of on-line signal bursts based upon measured phase errors and accelerated predicted phase gain and preemphasis phase errors.
    Type: Application
    Filed: May 9, 2003
    Publication date: November 11, 2004
    Inventors: James E. C. Brown, Bret Rothenberg, Chienkuo Vincent Tien
  • Publication number: 20040223572
    Abstract: A method and apparatus for generating a burst FSK signal having precisely shaped transitions between modulation states. The apparatus uses feedforward compensation of phase gain and phase preemphasis coefficients for compensating the frequency conversion gain of the apparatus, and the phase gain coefficient is used for stabilizing a frequency synthesis loop. The phase gain and preemphasis coefficients are determined in a calibration within the time constraints of on-line signal bursts based upon measured phase errors and accelerated predicted phase gain and preemphasis phase errors.
    Type: Application
    Filed: May 9, 2003
    Publication date: November 11, 2004
    Inventors: James E. C. Brown, Bret Rothenberg
  • Publication number: 20040146121
    Abstract: A method and apparatus for balancing I/Q gain and I/Q phase in a signal receiver. The receiver includes an IQ coefficient calculator and an IQ balancer. The IQ coefficient calculator computes a set of correction coefficients for each packet from the I and Q signals in an IQ measurement section at the front of the packet. The IQ balancer uses the correction coefficients for correcting the I/Q gain and I/Q phase errors on a packet-by-packet basis. Optionally, delay devices delay the I and Q signals so that the correction coefficients may be applied to the entire packet, or the portion of the packet in the IQ measurement section is passed through uncorrected and the correction coefficients are applied to the packet after the IQ measurement section.
    Type: Application
    Filed: August 7, 2003
    Publication date: July 29, 2004
    Inventors: James E. C. Brown, Bret Rothenberg