Abstract: A servo loop control apparatus having a master microprocessor and at least one autonomous streamlined signal processor is disclosed. The architecture provides a general purpose controller for use in systems where intensive servo signal processing is required and is well suited to applications where multiple servo control loops operate simultaneously. The operation of the streamlined signal processors is autonomous from the master processor so that critical functions can be dedicated to the streamlined signal processors. This eliminates complex interrupt management and tedious real time scheduling constraints, simplifies system design and improves system performance. The architecture provides an integrated mechanism for implementing multiple, concurrent, complex signal processing and embedded control functions, such as complete servo-mechanism management for high performance disk storage systems.

Abstract: A servo loop control apparatus having a master microprocessor and at least one autonomous streamlined signal processor is disclosed. The architecture provides a general purpose controller for use in systems where intensive servo signal processing is required and is well suited to applications where multiple servo control loops operate simultaneously. The operation of the streamlined signal processors is autonomous from the master processor so that critical functions can be dedicated to the streamlined signal processors. This eliminates complex interrupt management and tedious real time scheduling constraints, simplifies system design and improves system performance. The architecture provides an integrated mechanism for implementing multiple, concurrent, complex signal processing and embedded control functions, such as complete servo-mechanism management for high performance disk storage systems.

Abstract: An interrupt vector approach for a processor system loads an interrupt vector directly into an address. register to minimize overhead of processing interrupts. A plurality of interrupt triggers correspond to a plurality of interrupt vector registers, each containing a programmable interrupt vector. Upon activation of one of the interrupt triggers, the contents of the corresponding interrupt vector is loaded into a slot memory address counter. The address counter addresses a sequencer slot memory which contains the starting addresses of sequences of instructions stored in an instruction memory. An instruction address counter receives addresses from the sequencer slot memory and provides addresses to the instruction memory.

Abstract: A servo loop control apparatus having a master microprocessor and at least one autonomous streamlined signal processor is disclosed. The architecture provides a general purpose controller for use in systems where intensive servo signal processing is required and is well suited to applications where multiple servo control loops operate simultaneously. The operation of the streamlined signal processors is autonomous from the master processor so that critical functions can be dedicated to the streamlined signal processors. This eliminates complex interrupt management and tedious real time scheduling constraints, simplifies system design and improves system performance. The architecture provides an integrated mechanism for implementing multiple, concurrent, complex signal processing and embedded control functions, such as complete servo-mechanism management for high performance disk storage systems.

Abstract: An interrupt vector approach for a processor system loads an interrupt vector directly into an address register to minimize overhead of processing interrupts. A plurality of interrupt triggers correspond to a plurality of interrupt vector registers, each containing a programmable interrupt vector. Upon activation of one of the interrupt triggers, the contents of the corresponding interrupt vector is loaded into a slot memory address counter. The address counter addresses a sequencer slot memory which contains the starting addresses of sequences of instructions stored in an instruction memory. An instruction address counter receives addresses from the sequencer slot memory and provides addresses to the instruction memory.

Abstract: An interrupt vector approach for a processor system loads an interrupt vector directly into an address register to minimize overhead of processing interrupts. A plurality of interrupt triggers correspond to a plurality of interrupt vector registers, each containing a programmable interrupt vector. Upon activation of one of the interrupt triggers, the contents of the corresponding interrupt vector is loaded into a slot memory address counter. The address counter addresses a sequencer slot memory which contains the starting addresses of sequences of instructions stored in an instruction memory. An instruction address counter receives addresses from the sequencer slot memory and provides addresses to the instruction memory.

Abstract: Analog to digital conversion of signals at rates higher than can be accomplished by a monolithic flash analog to digital converter is achieved using multiple flash analog to digital converters operated in a parallel architecture. Sample timing of the multiple converters is skewed by selecting subfrequencies of a control clock or different phases of a control clock as the source for the sample control signal. The multiple flash converter outputs are then digitally recombined to produce a single output identical to a flash converter operating at a higher speed than could be obtained for a given set of circuit parameters.

Abstract: A converter circuit provides analog to digital and digital to analog functions on a single silicon device. A flash analog to digital converter produces digital outputs using comparators which each receive an input signal and which each have different reference voltages. A decoder receiving digital inputs activates switches to connect selected ones of the same voltage references used by the flash analog to digital converter to a buffer which produces an analog output. The converter circuit can be a single or multi-stage flash analog to digital converter operating in a single channel or multi-channel environment. Timing and control logic prevents switching from occurring at times when perturbations on the voltage references could affect the analog and digital outputs.