Patents by Inventor Brian D. Possley

Brian D. Possley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7327370
    Abstract: A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: February 5, 2008
    Assignee: Intel Corporation
    Inventors: Brian D. Possley, David M. Puffer, Kurt B. Robinson, Ray Askew, James S. Chapple, Thomas E. Dever, II
  • Patent number: 7116331
    Abstract: A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data, and interface circuitry adapted selectively to couple the graphics subsystem to a local memory through electrical connectors and to couple the memory controller hub to a graphics controller through the electrical connectors.
    Type: Grant
    Filed: August 23, 2000
    Date of Patent: October 3, 2006
    Assignee: Intel Corporation
    Inventors: Brian D. Possley, David M. Puffer, Kurt B. Robinson, Ray Askew, James S. Chapple, Thomas E. Dever, II
  • Patent number: 6974978
    Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes a semiconductor substrate having a plurality of N-type diffusion regions and P-type diffusion regions. The diffusion regions have partially overlying polysilicon landing sites to form N-type and P-type transistors. The regions are relatively sized to form two distinct transistor sizes, smaller N- and P-type transistors and larger N- and P-type transistors.
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventor: Brian D. Possley
  • Patent number: 6753209
    Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes a semiconductor substrate having a plurality of N-type diffusion regions and P-type diffusion regions. The diffusion regions have partially overlying polysilicon landing sites to form N-type and P-type transistors. The regions are relatively sized to form two distinct transistor sizes, smaller N- and P-type transistors and larger N- and P-type transistors.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: June 22, 2004
    Assignee: Intel Corporation
    Inventor: Brian D. Possley
  • Publication number: 20020074570
    Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes a semiconductor substrate having a plurality of N-type diffusion regions and P-type diffusion regions. The diffusion regions have partially overlying polysilicon landing sites to form N-type and P-type transistors. The regions are relatively sized to form two distinct transistor sizes, smaller N- and P-type transistors and larger N- and P-type transistors.
    Type: Application
    Filed: July 10, 2001
    Publication date: June 20, 2002
    Inventor: Brian D. Possley
  • Publication number: 20020070391
    Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes a semiconductor substrate having a plurality of N-type diffusion regions and P-type diffusion regions. The diffusion regions have partially overlying polysilicon landing sites to form N-type and P-type transistors. The regions are relatively sized to form two distinct transistor sizes, smaller N- and P-type transistors and larger N- and P-type transistors.
    Type: Application
    Filed: July 10, 2001
    Publication date: June 13, 2002
    Inventor: Brian D. Possley