Abstract: A system and method are provided for periodically servicing a channel in a timer used for controlling events. The method services a channel in a fixed periodic cycle, and reads a first control word loaded in the channel to determine a timer operation. Then, a first data word in the channel is managed in response to the determined operation. In one aspect, a clock signal is supplied with a fixed period. Then, servicing the channel in a fixed periodic cycle includes: establishing a cycle having a first number of clock signals; and, servicing the channel for a second number of clock signals each cycle. If the timer includes a plurality of channels, then each channel is serially serviced in a single cycle.

Abstract: A timer system comprises multiple channels, each of which is capable of performing input and output timer functions referenced to any of a plurality of timer reference signals. In the preferred embodiment, sixteen independent channels are serviced by a processor dedicated to that purpose and each can perform capture and match functions referenced to either of two free-running counters.

Abstract: An interrupt priority circuit is used with a data processor which is responsive to interrupt signals from each of a plurality of resources of predetermined priority. A priority encoder receives all of the interrupt signals, and provides an interrupt vector corresponding to the interrupt signal received from the resource having the highest predetermined priority. However, the interrupt priority of a selected resource may be dynamically altered to the highest priority by storing a corresponding priority vector into a priority register. A first multiplexor controlled by the priority vector provides an enable signal whenever an interrupt signal is received from the selected resource. A second multiplexor controlled by the enable signal provides the priority vector if the enable signal is present or the interrupt vector otherwise. A gate controlled by the data processor may be provided to selectively couple the vector provided by the second multiplexor onto the address bus.

Abstract: A timer channel with multiple timer reference signals available to it which is capable of performing any input or output timer function with reference to any of the available reference signals. In addition, input timer functions may be related to the occurrence of output functions. For instance, the state of one timer reference may be captured automatically at a specified time referenced to another timer reference. Another feature of the invention provides for the creation of a time-out window for an input timer function through the use of a concurrent output function.

Abstract: A timer system comprises multiple channels, each of which is capable of performing input and output timer functions referenced to any of a plurality of timer reference signals. In the preferred embodiment, sixteen independent channels are serviced by a processor dedicated to that purpose and each can perform capture and match functions referenced to either of two free-running counters.

Abstract: A write protect mechanism for a programmable read-only memory prevents writes to the PROM unless a protect register contains predetermined information. The protect register is itself a write protected control register. The predetermined information cannot be written into the protect register except during a short, predetermined period after the occurrence of an event such as a reset. The protect register may be written to with information other than the predetermined information at any time. The preferred embodiment comprises a single-chip microcomputer with on-board electrically-erasable programmable read-only memory which is write protected in several, separate blocks.

Abstract: A single-chip microcomputer comprises at least two separate and independent electrically erasable programmable read only memories (EEPROMs) on-board which may be independently programmed, erased and read. Each part of the split EEPROM has its own data bus and address bus. Programming and erasing is controlled by a program register which has separate bits for configuring and latching the data and address buses of a selected EEPROM array, for providing programming voltage to the array of choice and for choosing between programming and erasing the selected array. The split EEPROM provides versatility to the user in allowing one part of the EEPROM to be programmed while the program stored in another part of the EEPROM or RAM may be read and utilized. In addition, test time and effort of the microcomputer may be considerably reduced.

Abstract: An integrated circuit microcomputer with EEPROM has a limited number of modes for operation. In at least first and second modes, the inner workings of the microcomputer, including the contents of the EEPROM, can be read externally from the microcomputer. An EEPROM security bit, when set, prevents the first mode from being entered and causes the EEPROM to be erased when the second mode is entered. The EEPROM is also erased if the security bit is erased.