Abstract: An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

Abstract: A structure and method for fabricating a transistor structure is provided. The method comprises the steps of: (a) providing a substrate including a semiconductor-on-insulator (“SOI”) layer separated from a bulk region of the substrate by a buried dielectric layer. (b) first implanting the SOI layer to achieve a predetermined dopant concentration at an interface of the SOI layer to the buried dielectric layer. and (c) second implanting said SOI layer to achieve predetermined dopant concentrations in a polycrystalline semiconductor gate conductor (“poly gate”) and in source and drain regions disposed adjacent to the poly gate, wherein a maximum depth of the first implanting is greater than a maximum depth of the second implanting.

Abstract: Integrated circuits are oriented on a substrate at an angle that is rotated between 5 to 40 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.

Abstract: A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

Abstract: An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses.

Abstract: Methods of fabricating a semiconductor structure including heterogeneous suicides or germanides located in different regions of a semiconductor structure are provided. The heterogeneous suicides or germanides are formed onto a semiconductor layer, a conductive layer or both. In accordance with the present invention, the inventive methods utilize a combination of sequential deposition of different metals and patterning to form different suicides or germanides in different regions of a semiconductor chip. The method includes providing a Si-containing or Ge layer having at least a first region and a second region; forming a first silicide or germanide on one of the first or second regions; and forming a second silicide or germanide that is compositionally different from the first silicide or germanide on the other region not including the first silicide or germanide, wherein the steps of forming the first and second suicides or germanides are performed sequentially or in a single step.

Abstract: A compressive stress is applied to a channel region of a PFET by structure including a discrete dielectric stressor element that fully underlies the bottom surface of an active semiconductor region in which the source, drain and channel region of the PFET is disposed. In particular, the dielectric stressor element includes a region of collapsed oxide which fully contacts the bottom surface of the active semiconductor region such that it has an area coextensive with an area of the bottom surface. Bird's beak oxide regions at edges of the dielectric stressor element apply an upward force at edges of the dielectric stressor element to impart a compressive stress to the channel region of the PFET.

Abstract: A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A buried dielectric stressor element has a horizontally extending upper surface at a first depth below a major surface of a portion of the active semiconductor region, such as an east portion of the active semiconductor region. A surface dielectric stressor element is disposed laterally adjacent to the active semiconductor region at the major surface of the active semiconductor region. The surface dielectric stressor element extends from the major surface to a second depth not substantially greater than the first depth.

Abstract: A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A dielectric stressor element having a horizontally extending upper surface extends below a portion of the active semiconductor region. The dielectric stressor element shares an edge with the active semiconductor region, the edge extending in a direction away from the upper surface. In particular structures, two or more dielectric stressor elements are provided at locations opposite from each other in the longitudinal and/or transverse directions of the FET.

Abstract: A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A first dielectric stressor element having a horizontally extending upper surface extends below a portion of the active semiconductor region, such as a northwest portion of the active semiconductor region. A second dielectric stressor element having a horizontally extending upper surface extends below a second portion of the active semiconductor region, such as a southeast portion of the active semiconductor region. Each of the first and second dielectric stressor elements shares an edge with the active semiconductor region, the edges extending in directions away from the upper surface.

Abstract: A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer.

Abstract: A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. An ultra-thin (UT) semiconductor-on-insulator channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A first BOX region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a second BOX region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.

Abstract: Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.

Abstract: The example embodiments disclose devices and methods to prevent silicide strapping of the Source/Drain to Body in semiconductor devices with S/D stressor. We provide isolation regions in the substrate and a gate structure over the substrate. We form recesses in the substrate adjacent to the gate structure with disposable spacers and adjacent to the isolation regions. We provide stressor regions filling the recesses. The stress region can have a pit adjacent the isolation regions. We form stressor spacers at least partially in the pit on the sidewalls of the stressor regions. We form silicide regions over the stressor regions. The spacer on the stressor regions sidewalls inhibit the formation of silicide at the stressor region edge during the silicide process, thus preventing silicide strapping of the Source/Drain to Body.

Abstract: The present invention provides a technique for forming a CMOS structure including at least one pFET that has a stressed channel which avoids the problems mentioned in the prior art. Specifically, the present invention provides a method for avoiding formation of deep canyons at the interface between the active area and the trench isolation region, without requiring a trench isolation pulldown, thereby eliminating the problems of silicide to source/drain shorts and contact issues. At the same time, the method of the present invention provides a structure that allows for a facet to form at the spacer edge, retaining the Miller capacitance benefit that such a structure provides. The inventive structure also results in higher uniaxial stress in the MOSFET channel compared to one which allows for a facet to grow at the trench isolation edge.

Abstract: Form a dielectric layer on a semiconductor substrate. Deposit an amorphous Si film or a poly-Si film on the dielectric layer. Then deposit a SiGe amorphous-Ge or polysilicon-Ge thin film theteover. Pattern and etch the SiGe film using a selective etch leaving the SiGe thin film intact in a PFET region and removing the SiGe film exposing the top surface of the Si film in an NFET region. Anneal to drive Ge into the Si film in the PFET region. Deposit a gate electrode layer covering the SiGe film in the PFET region and cover the exposed portion of the Si film in the NFET region. Pattern and etch the gate electrode layer to form gates. Form FET devices with sidewall spacers and source regions and drains regions in the substrate aligned with the gates.

Abstract: Integrated circuits are oriented on a substrate at an angle that is rotated between 0 to 45 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.

Abstract: A test structure of a semiconductor device is provided. The test structure includes a semiconductor substrate, a transistor which includes a gate electrode formed on first and second active regions defined within the semiconductor substrate, and first and second junction regions which are arranged at both sidewalls of the gate electrode to reside within the first and second active regions and are silicided, and first and second pads through which electrical signals are applied to the silicided first and second junction regions and detected and which are formed on the same level as the gate electrode or the semiconductor substrate.

Abstract: A test structure of a semiconductor device with improved test reliability is provided. The test structure includes first and second active regions which are electrically isolated from each other and on which silicided first and second junction regions are formed, respectively, a semiconductor substrate or a well which is formed on lower parts of the first and second junction regions and has a conductivity type different from the first and second junction regions, and first and second pads through which an electrical signal is applied to the first and second junction regions and detected, and which are formed on the same level as a lower part of a metal layer or on the same level as the semiconductor substrate.

Abstract: The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.