Patents by Inventor Brian K. Butler

Brian K. Butler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5774496
    Abstract: A system for determining the rate at which data has been encoded in the receiver of a variable-rate communications system. The data is received in frames having a fixed number of symbols. Multiple copies of symbols fill the frame when data is encoded at less than the full rate. At an encoding rate of one fourth the full rate, for example, each symbol in the frame is repeated four times. The incoming symbols are provided to multiple paths for decoding. Each path decodes the symbols at one of the possible rates. Error metrics, which describe the quality of the decoded symbols, are extracted and provided to a processor. The error metrics may include Cyclic Redundancy Check (CRC) results, Yamamoto Quality Metrics, and Symbol Error Rates. The processor analyzes the error metrics and determines the most probable rate at which the incoming symbols were encoded.
    Type: Grant
    Filed: June 4, 1996
    Date of Patent: June 30, 1998
    Assignee: QUALCOMM Incorporated
    Inventors: Brian K. Butler, Roberto Padovani, Ephraim Zehavi
  • Patent number: 5710521
    Abstract: A system for substantially eliminating nonlinear distortion, such as intermodulation products, introduced when a signal is processed by a nonlinear device. The system adds an out-of-band signal to an input signal to produce a combined signal having a power that substantially equals a nominal operating point power for a nonlinear device. Preferably, the instantaneous power of the out-of-band signal is adjusted by an automatic gain amplifier. The combined signal is input to the nonlinear device to produce an output. A filter processes the output of the nonlinear device to recover the information content of the original signal after processing by the nonlinear device. For example, if the nonlinear device is a power amplifier, the filtered output is an amplification of the input signal.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: January 20, 1998
    Assignee: Qualcomm Incorporated
    Inventor: Brian K. Butler
  • Patent number: 5710784
    Abstract: A Viterbi decoder for recovering the original bit data stream that was convolutionally encoded as a code symbol stream in a Code Division Multiple Access (CDMA) mobile communication system. The decoder simultaneously decodes at the several data rates associated with certain multirate vocoders. The decoder can decode at an unknown data rate in either continuous or framed packet modes. It accomplishes this by simultaneously decoding at multiple rates and by creating one or more data quality metrics for each decoded data packet. Special input and output buffering is provided to isolate the decoder from system timing constraints. The input buffer includes selection and accumulation logic to organize code symbol data into the packet order for repeat mode or random burst mode at lower frame data rates.
    Type: Grant
    Filed: October 9, 1996
    Date of Patent: January 20, 1998
    Assignee: Qualcomm Incorporated
    Inventors: Daniel Ray Kindred, Brian K. Butler, Ephraim Zehavi, Jack Keil Wolf
  • Patent number: 5566206
    Abstract: A system for determining the rate at which data has been encoded in the receiver of a variable-rate communications system. The data is received in frames having a fixed number of symbols. Multiple copies of symbols fill the frame when data is encoded at less than the full rate. At an encoding rate of one fourth the full rate, for example, each symbol in the frame is repeated four times. The incoming symbols are provided to multiple paths for decoding. Each path decodes the symbols at one of the possible rates. Error metrics, which describe the quality of the decoded symbols, are extracted and provided to a processor. The error metrics may include Cyclic Redundancy Check (CRC) results, Yamamoto Quality Metrics, and Symbol Error Rates. The processor analyzes the error metrics and determines the most probable rate at which the incoming symbols were encoded.
    Type: Grant
    Filed: April 26, 1994
    Date of Patent: October 15, 1996
    Assignee: QUALCOMM Incorporated
    Inventors: Brian K. Butler, Roberto Padovani, Ephraim Zehavi
  • Patent number: 5511073
    Abstract: A method and apparatus for arranging various types of data, and at various rates, into a uniquely structured format for transmission. Data for transmission formatting may be vocoder data or different types of non-vocoder data. The data organized into frames of a predetermined time duration for transmission. The data frames are organized, depending on the data, to be at one of several data rates. Vocoder data is provided at one of several data rates and is organized in the frame according to a predetermined format. Frames may be formatted with a sharing of vocoder data with non-vocoder data to be at a highest frame data rate. Different types of non-vocoder data may be organized so as to also be at the highest frame data rate. Additional control data may be provided within the data frames to support various aspects of the transmission and recovery upon reception.
    Type: Grant
    Filed: September 7, 1993
    Date of Patent: April 23, 1996
    Assignee: Qualcomm Incorporated
    Inventors: Roberto Padovani, Edward G. Tiedemann, Jr., Lindsay A. Weaver, Jr., Brian K. Butler
  • Patent number: 5504773
    Abstract: In a digital communication system in which digital data is transmitted in data frames of a preselected time duration, a method and apparatus for formatting digital data in each data frame. A set of data bits of a first data type having a bit count corresponding to one of a plurality of predetermined bit counts are provided. A set of parity check bits for the set of data bits of said first data type are generated when the bit count is a highest bit count or a next to highest bit count. A set of tail bits is generated in accordance with a predetermined frame termination format. In respective order the set of data bits of the first data type, the parity check bits, and the tail bits are porovided in a data frame if the bit count is of the highest bit count or of the next to highest bit count. Otherwise, the set of data bits of the first data type and the tail bits are provided in respective order in the data frame.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: April 2, 1996
    Assignee: Qualcomm Incorporated
    Inventors: Roberto Padovani, Edward G. Tiedemann, Jr., Lindsay A. Weaver, Jr., Brian K. Butler