Patents by Inventor Brian K. Forbes
Brian K. Forbes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5708810Abstract: An image-based document processing system comprised of a plurality of hardware components arranged as a platform for processing documents using document images. The system employs a layered software architecture comprised of application programs, system services and a plurality of native operating systems provided for particular ones of the hardware components. The system services are callable by the application programs to provide an interface between the application programs and the native operating systems during operation of the system.Type: GrantFiled: December 9, 1991Date of Patent: January 13, 1998Assignee: Unisys CorporationInventors: Norman P. Kern, Brian K. Forbes, John G. Hemmann, James D. Rogan, Morten Wiken, Joseph M. Capo, Howard H. Green
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Patent number: 5321816Abstract: An apparatus provides a network combining a local site having a host computer and a specialized storage and retrieval module for storing image information which is connected to a remote site having document processing equipment working with remote specialized storage retrieval modules for storage of image and information data. The single local main host computer can operate the network such that documents which are converted to digitized packets can be stored in and retrieved from both the remote storage retrieval modules and also stored int eh local storage retrieval module for use of the remote and the local peripheral devices.Type: GrantFiled: December 9, 1992Date of Patent: June 14, 1994Assignee: Unisys CorporationInventors: James D. Rogan, Brian K. Forbes, Michael G. Birdsall
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Patent number: 4507732Abstract: An I/O subsystem uses a peripheral-controller for handling data transfer operations between a host computer and a plurality of peripheral terminals. The peripheral controller is made of (a) a universal processor, which generates instructions for executing data transfer operations, and (b) an application dependent logic module which particularly adapts the instructions to each peripheral terminal connected to the system. Upon recognition of the use of addresses for slow memories, slow registers or "slow devices", control logic in the application dependent logic module controls the clocking in the universal processor to slow data transfer rates for data being placed in or removed from the "slow devices".Type: GrantFiled: September 7, 1983Date of Patent: March 26, 1985Assignee: Burroughs CorporationInventors: Robert D. Catiller, Brian K. Forbes
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Patent number: 4456970Abstract: An interrupt network whereby, upon completion of a data transfer cycle between a host computer and peripheral-controller or completion of a data transfer cycle between a peripheral terminal and peripheral-controller, the peripheral-controller is placed in an interrupt mode (background mode) and institutes an interrupt service routine. The normal mode data in the peripheral-controller is stored for re-use upon return to normal mode.Type: GrantFiled: December 10, 1981Date of Patent: June 26, 1984Assignee: Burroughs CorporationInventors: Robert D. Catiller, Brian K. Forbes
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Patent number: 4379328Abstract: A microprocessor system in which a microprocessor with a linear sequencing circuit works with arithmetic logic, program memory, registers, and other support circuitry to provide control lines and bus connections to an external application dependent logic module which has control logic, external registers and external memory and is oriented to handle the specific requirements for data transfers to and from a particular type of peripheral device. Means are provided in said microprocessor for selecting the number of times an instruction word is to be repeated and for the halting of a repeated instruction by internal or external means.Type: GrantFiled: December 15, 1980Date of Patent: April 5, 1983Assignee: Burroughs CorporationInventors: Robert D. Catiller, Brian K. Forbes
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Patent number: 4374416Abstract: A microprocessor system having linear program sequencing and working in conjunction with an application dependent logic module tailored to handle the requirements of a variety of types of peripheral devices and wherein a microprocessor operates as a universal standard for all types of different application dependent logic modules. Means are provided for the microprocessor to access a total word from memory or to access any selected byte of a word in memory. Thus, the microprocessor and the application dependent logic module constitute a peripheral-controller which can control and monitor data transfer operations between a main host computer and a variety of peripheral devices whether such peripheral devices are "byte" oriented, such as card readers, or whether the peripheral terminal unit is "word" oriented such as magnetic tape or disk peripheral units.Type: GrantFiled: December 15, 1980Date of Patent: February 15, 1983Assignee: Burroughs CorporationInventors: Robert D. Catiller, Brian K. Forbes
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Patent number: 4374418Abstract: A microprocessor system works in conjunction with an application dependent logic module tailored to serve the particular requirements of a given peripheral device. The microprocessor is provided with a linear microsequencer circuit to operate with all types of application dependent logic modules and to provide instructions and control for data transfer operations. Means are provided in the microprocessor for operation in a "normal" mode whereby a first set of accumulator registers and flag registers are used exclusively, and in a "background" or interrupt mode where a second set of accumulator registers and flag registers are used exclusively.Type: GrantFiled: March 5, 1981Date of Patent: February 15, 1983Assignee: Burroughs CorporationInventors: Robert D. Catiller, Brian K. Forbes
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Patent number: 4371931Abstract: A microprocessor system comprising an arithmetical logic unit, a program memory and an external memory, memory address means (including a program counter and a memory reference register) for addressing either the program memory or the external memory. The microprocessor is sequenced by a linear sequencing circuit which can use different size plug-compatible PROMs. An instruction register receives instructions from either program memory or external memory along an instruction bus, which instructions are conveyed via a memory operand register to the arithmetic logic unit. The program memory is provided with a specialized instruction word format. The instruction word format provides: a single bit field for selecting either the program counter or the memory reference register as the source of memory addresses; it provides a function field which defines the route of data transfers to be made; and provides a "source and destination" field for addressing selected source and destination locations.Type: GrantFiled: March 5, 1981Date of Patent: February 1, 1983Assignee: Burroughs CorporationInventors: Robert D. Catiller, Brian K. Forbes
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Patent number: 4301505Abstract: A microprocessor system working in conjunction with an application dependent logic module tailored to handle the requirements of a variety of types of peripheral devices and wherein a microprocessor operates as a universal standard for all types of different application dependent logic modules. Means are provided for the microprocessor to access a total word from memory or to access any selected byte of a word in memory. Thus, the microprocessor and the application dependent logic module constitute a peripheral-controller which can control and monitor data transfer operations between a main host computer and a variety of peripheral devices whether such peripheral devices are "byte" oriented, such as card readers, or whether the peripheral terminal unit is "word" oriented such as magnetic tape or disk peripheral units.Type: GrantFiled: June 27, 1979Date of Patent: November 17, 1981Assignee: Burroughs CorporationInventors: Robert D. Catiller, Brian K. Forbes
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Patent number: 4293909Abstract: A digital system which a main host computer is connected for communication with a plurality of base modules. Each base module supports a plurality of peripheral-controllers which include an application dependent logic module for handling the specific needs in data transfers to/from a particular type of peripheral device. Each peripheral-controller comprises a universal standardized microprocessor which works in conjunction with said application dependent logic module. Means are provided in the microprocessor and the microprocessor system operating with said application dependent logic module to control and handle data transfer functions between said main host computer system and remote peripheral devices.Type: GrantFiled: June 27, 1979Date of Patent: October 6, 1981Assignee: Burroughs CorporationInventors: Robert D. Catiller, Brian K. Forbes
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Patent number: 4292667Abstract: A microprocessor system in which a microprocessor having arithmetic logic, program memory, registers, and other support circuitry provides control lines and bus connections to an external application dependent logic module which has control logic, external registers and external memory and is oriented to handle the specific requirements for data transfers to and from a particular type of peripheral device. Means are provided in said microprocessor for selecting the number of times an instruction word is to be repeated and for the halting of a repeated instruction.Type: GrantFiled: June 27, 1979Date of Patent: September 29, 1981Assignee: Burroughs CorporationInventors: Robert D. Catiller, Brian K. Forbes
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Patent number: 4291372Abstract: A microprocessor system which works in conjunction with an external application dependent logic module which logic module handles the specific requirements for data transfer to and from a peripheral device. The system includes a microprocessor which provides a program memory having a specialized instruction format. The instruction word format provides a single bit field for selecting either a program counter or a memory reference register as the source of memory addresses, a function field which defines the route of data transfers to be made, and a source and destination field for addressing source and destination locations.Type: GrantFiled: June 27, 1979Date of Patent: September 22, 1981Assignee: Burroughs CorporationInventors: Brian K. Forbes, Robert D. Catiller
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Patent number: 4290106Abstract: A microprocessor system having control lines and bus connections to an application dependent logic module having control logic, external registers and external memory for data transfers to/from a specific type of peripheral device. Addressing means are provided in said microprocessor whereby a program counter is used to address program memory and a memory reference register is used to provide addresses for access to external memory, and said memory reference register includes a low order bit field which selects whether the program counter or the memory reference register will be the address source for memory accesses.Type: GrantFiled: June 27, 1979Date of Patent: September 15, 1981Assignee: Burroughs CorporationInventors: Robert D. Catiller, Brian K. Forbes
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Patent number: 4287560Abstract: A microprocessor system working in conjunction with an application dependent logic module tailored to serve the particular requirements of a given peripheral device. A microprocessor of a uniform architecture works in conjunction with all types of application dependent logic modules to provide instructions and control for data transfer operations. Means are provided in the microprocessor for operation in a normal mode whereby a first set of accumulator registers and flag registers are used exclusively and in a background or interrupt mode where a second set of accumulator registers and flag registers are used exclusively.Type: GrantFiled: June 27, 1979Date of Patent: September 1, 1981Assignee: Burroughs CorporationInventors: Brian K. Forbes, Robert D. Catiller