Abstract: A processor receives a signal and determines whether an application has registered a signal handler therewith for handling the signal. In response to determining that the application has registered the signal handler, the processor transmits the signal directly to the signal handler of the application for handling the signal, without an operating system in relation to which the trusted application is running intervening. In response to determining that the trusted application has not registered the signal handler, the processor transmits the signal to a signal handler of the operating system for handling the signal.

Abstract: A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode.

Abstract: Aspects of an embodiment of the invention disclose a method, computer program product, and system for managing the energy efficiency of servers providing multi-class computing services with Quality of Service (QoS) assurance. Computing resources are clustered into at least three groups, where each group has a separate power management policy (PMP). A plurality of requests are received from a plurality of devices, and are sorted into at least three service classes based on the requests' QoS criteria. Each request is assigned to one of at least three service queues based on the request's service class, and each service group is processed by a group of computing resources. The power management policies are configured such that each group of computing resources may service requests at an energy efficient point while meeting the QoS criteria of the service class.

Abstract: A processor receives a signal and determines whether an application has registered a signal handler therewith for handling the signal. In response to determining that the application has registered the signal handler, the processor transmits the signal directly to the signal handler of the application for handling the signal, without an operating system in relation to which the trusted application is running intervening. In response to determining that the trusted application has not registered the signal handler, the processor transmits the signal to a signal handler of the operating system for handling the signal.

Abstract: A processor receives a signal and determines whether an application has registered a signal handler therewith for handling the signal. In response to determining that the application has registered the signal handler, the processor transmits the signal directly to the signal handler of the application for handling the signal, without an operating system in relation to which the trusted application is running intervening. In response to determining that the trusted application has not registered the signal handler, the processor transmits the signal to a signal handler of the operating system for handling the signal.

Abstract: Aspects of an embodiment of the invention disclose a method, computer program product, and system for managing the energy efficiency of servers providing multi-class computing services with Quality of Service (QoS) assurance. Computing resources are clustered into at least three groups, where each group has a separate power management policy (PMP). A plurality of requests are received from a plurality of devices, and are sorted into at least three service classes based on the requests' QoS criteria. Each request is assigned to one of at least three service queues based on the request's service class, and each service group is processed by a group of computing resources. The power management policies are configured such that each group of computing resources may service requests at an energy efficient point while meeting the QoS criteria of the service class.

Abstract: Aspects of an embodiment of the invention disclose a method, computer program product, and system for managing the energy efficiency of servers providing multi-class computing services with Quality of Service (QoS) assurance. Computing resources are clustered into at least three groups, where each group has a separate power management policy (PMP). A plurality of requests are received from a plurality of devices, and are sorted into at least three service classes based on the requests' QoS criteria. Each request is assigned to one of at least three service queues based on the request's service class, and each service group is processed by a group of computing resources. The power management policies are configured such that each group of computing resources may service requests at an energy efficient point while meeting the QoS criteria of the service class.

Abstract: A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode.

Abstract: Technical solutions are described for determining a population count of an input bit-string. In an example, a population count circuit receives a single n-bit input data word including of bits A[n?1:0]. The population count circuit isolates a pair of 4-bit nibbles. The population count circuit includes a carryless counter circuit that determines a pair of counts of 1s, one for each 4-bit nibble. The population circuit further includes an adder circuit that determines the population count by summing the pair of counts of 1s from the carryless counter circuit, where the adder circuit determines the most significant bit (MSB) of the sum based on the MSBs of the counts of 1s only, without depending on carry propagation.

Abstract: A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode.

Abstract: Aspects of an embodiment of the invention disclose a method, computer program product, and system for managing the energy efficiency of servers providing multi-class computing services with Quality of Service (QoS) assurance. Computing resources are clustered into at least three groups, where each group has a separate power management policy (PMP). A plurality of requests are received from a plurality of devices, and are sorted into at least three service classes based on the requests' QoS criteria. Each request is assigned to one of at least three service queues based on the request's service class, and each service group is processed by a group of computing resources. The power management policies are configured such that each group of computing resources may service requests at an energy efficient point while meeting the QoS criteria of the service class.

Abstract: Aspects of an embodiment of the invention disclose a method, computer program product, and system for managing the energy efficiency of servers providing multi-class computing services with Quality of Service (QoS) assurance. Computing resources are clustered into at least three groups, where each group has a separate power management policy (PMP). A plurality of requests are received from a plurality of devices, and are sorted into at least three service classes based on the requests' QoS criteria. Each request is assigned to one of at least three service queues based on the request's service class, and each service group is processed by a group of computing resources. The power management policies are configured such that each group of computing resources may service requests at an energy efficient point while meeting the QoS criteria of the service class.

Abstract: Technical solutions are described for determining a population count of an input bit-string. In an example, a population count circuit receives a single n-bit input data word including of bits A[n?1:0]. The population count circuit isolates a pair of 4-bit nibbles. The population count circuit includes a carryless counter circuit that determines a pair of counts of 1s, one for each 4-bit nibble. The population circuit further includes an adder circuit that determines the population count by summing the pair of counts of 1s from the carryless counter circuit, where the adder circuit determines the most significant bit (MSB) of the sum based on the MSBs of the counts of 1s only, without depending on carry propagation.

Abstract: A method for managing processor power optimization is provided. The method may include receiving a plurality of tasks for processing by a processor environment. The method may also include allocating a portion of a compute resource corresponding to the processor environment to each of the received plurality of tasks, the allocating of the portion being based on both an execution time and a response time associated with each of the received plurality of tasks.

Abstract: Branch prediction for indirect jumps, including: receiving, by a branch prediction module, a branch address for each of a plurality of executed branch instructions; receiving, by the branch prediction module, an instruction address of a current branch instruction; creating, by the branch prediction module, an execution path identifier in dependence upon the branch address for each of the plurality of executed branch instructions and the instruction address of the current branch instruction; and searching, by the branch prediction module, a branch prediction table for an entry that matches the execution path identifier.

Abstract: Filtering snoop traffic in a multiprocessor computing system, each processor in the multiprocessor computing system coupled to a high level cache and a low level cache, the including: receiving a snoop message that identifies an address in shared memory targeted by a write operation; identifying a set in the high level cache that maps to the address in shared memory; determining whether the high level cache includes an entry associated with the address in shared memory; responsive to determining that the high level cache does not include an entry corresponding to the address in shared memory: determining whether the set in the high level cache has been bypassed by an entry in the low level cache; and responsive to determining that the set in the high level cache has not been bypassed by an entry in the low level cache, discarding the snoop message.

Abstract: A processor receives a signal and determines whether an application has registered a signal handler therewith for handling the signal. In response to determining that the application has registered the signal handler, the processor transmits the signal directly to the signal handler of the application for handling the signal, without an operating system in relation to which the trusted application is running intervening. In response to determining that the trusted application has not registered the signal handler, the processor transmits the signal to a signal handler of the operating system for handling the signal.

Abstract: A processor receives a signal and determines whether an application has registered a signal handler therewith for handling the signal. In response to determining that the application has registered the signal handler, the processor transmits the signal directly to the signal handler of the application for handling the signal, without an operating system in relation to which the trusted application is running intervening. In response to determining that the trusted application has not registered the signal handler, the processor transmits the signal to a signal handler of the operating system for handling the signal.

Abstract: An apparatus for lock acquisition is disclosed. A method and a computer program product also perform the functions of the apparatus. The apparatus includes a lock history module that adds a current contention state of a lock to a contention history. The lock includes a memory location for storing information used for excluding access to a resource by one or more threads while another thread accesses the resource. The apparatus, in some embodiments, includes a combination module that combines the contention history with a lock address for the lock to form a predictor table index, and a prediction module that uses the predictor table index to determine a lock prediction for the lock. The prediction includes a determination of an amount of contention.

Abstract: A method for lock acquisition includes adding a current contention state of a lock to a contention history. The lock includes a memory location for storing information used for excluding accessing a resource by one or more threads while another thread accesses the resource. The method includes combining the contention history with a lock address for the lock to form a predictor table index, and using the predictor table index to determine a lock prediction for the lock. The prediction includes a determination of an amount of contention.