Patents by Inventor Brian P. Erisman

Brian P. Erisman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6961396
    Abstract: A digital blanking circuit allows a first digital input signal transition to be passed on to a following stage, but prohibits the passing of subsequent transitions for a predetermined blanking interval. One embodiment of the present invention employs rising edge and falling edge latches, the inputs of which receive the digital input signal and the outputs of which are connected to a two-to-one multiplexer. The mux output is connected to a blanking interval circuit, which is triggered to begin timing a blanking interval by a multiplexer output transition. The blanking interval circuit provides outputs which control the latches and selects the latch output to be transferred to the multiplexer output such that the multiplexer output is prevented from transitioning during a blanking interval.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: November 1, 2005
    Assignee: Analog Devices, Inc.
    Inventors: Jonathan M. Audy, Gabor Reizik, Richard Redl, Brian P. Erisman
  • Patent number: 6879136
    Abstract: An inductor current emulation circuit for a switched-mode power supply (SMPS) which is arranged such that its inductor current (IL) goes to zero at least once per switching cycle. The emulation circuit includes an RC integrator connected in parallel across the inductor, and a zero reset switch (ZRS) connected in parallel across the integrator's capacitor. A control circuit operates the ZRS such that it is opened when IL is non-zero, and is closed for a least a portion of the time during each switching cycle when IL is zero such that the capacitor is substantially discharged. In this way, the ZRS essentially recalibrates the emulation circuit when IL is zero. When so arranged, the voltage (VC) across the capacitor emulates IL. The invention may be implemented with either a discontinuous-inductor-current SMPS, or a continuous-bipolar-inductor-current SMPS.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: April 12, 2005
    Assignee: Analog Devices, Inc.
    Inventors: Brian P. Erisman, Richard Redl
  • Publication number: 20020101945
    Abstract: A digital blanking circuit allows a first digital input signal transition to be passed on to a following stage, but prohibits the passing of subsequent transitions for a predetermined blanking interval. One embodiment of the present invention employs rising edge and falling edge latches, the inputs of which receive the digital input signal and the outputs of which are connected to a two-to-one multiplexer. The mux output is connected to a blanking interval circuit, which is triggered to begin timing a blanking interval by a multiplexer output transition. The blanking interval circuit provides outputs which control the latches and selects the latch output to be transferred to the multiplexer output such that the multiplexer output is prevented from transitioning during a blanking interval.
    Type: Application
    Filed: January 26, 2001
    Publication date: August 1, 2002
    Applicant: ANALOG DEVICES, INC.
    Inventors: Jonathan M. Audy, Richard Redl, Gabor Reizik, Brian P. Erisman
  • Patent number: 6229292
    Abstract: A method and circuit enable a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within specified boundaries for large bidirectional step changes in load current. This is achieved with a technique referred to as “optimal voltage positioning”, which keeps the output voltage within the specified boundaries while employing an output capacitor which has a combination of the largest possible equivalent series resistance (ESR) and lowest possible capacitance that ensures that the peak voltage deviation for a step change in load current is no greater than the maximum allowed. The invention can be used with regulators subject to design requirements that specify a minimum time Tmin between load transients, and with those for which no Tmin is specified.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: May 8, 2001
    Assignee: Analog Devices, Inc.
    Inventors: Richard Redl, Brian P. Erisman, Jonathan M. Audy, Gabor Reizik
  • Patent number: 6064187
    Abstract: A method and circuit enable a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within specified boundaries for large bidirectional step changes in load current. This is achieved by employing an output capacitor which has a combination of the largest possible equivalent series resistance (ESR) and lowest possible capacitance that ensures that the peak voltage deviation for a step change in load current is no greater than the maximum allowed, and by compensating the regulator to ensure a response that is flat after the occurrence of the peak deviation. The invention is applicable to both switching and linear voltage regulators.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: May 16, 2000
    Assignee: Analog Devices, Inc.
    Inventors: Richard Redl, Brian P. Erisman, Jonathan M. Audy, Gabor Reizik
  • Patent number: 5675481
    Abstract: A MOSFET driven integrated circuit or other peripheral circuit interfaced to a controller that operates on the primary side of a DC to DC converter having a high input voltage relative to the supply voltage powering both the controller and the MOSFET driver or other peripheral circuit is controlled by an under-voltage lockout circuit to transition from a standby mode to a normal operating mode of the MOSFET driver or other peripheral circuit only when the supply voltage is sufficient to sustain normal operation and the driver or other peripheral circuit senses activity at an input that indicates that the controller has previously transitioned from a standby mode to a normal operating mode.
    Type: Grant
    Filed: March 4, 1996
    Date of Patent: October 7, 1997
    Assignee: Toko, Inc.
    Inventor: Brian P. Erisman
  • Patent number: 5499176
    Abstract: A signal isolator circuit employing a pulse transformer overcomes the disadvantages of both prior art opto-coupler and pulse transformer signal isolator circuits by employing an active signal retrieval circuit which, in a higher accuracy configuration, repetitively performs the following steps on the electrical side of the pulse transformer where the signal information is required: 1) drives a current pulse into the pulse transformer; 2) samples or detects the voltage across the pulse transformer after it has been stabilized; 3) holds or stores the sampled voltage for a full cycle of operation; and, if necessary, 4) filters the sampled signal. On the other electrical side of the pulse transformer, the retrieval circuitry is configured such that when the pulse transformer is being driven by the current pulse, the voltage will be clamped by the source signal reset.
    Type: Grant
    Filed: August 12, 1993
    Date of Patent: March 12, 1996
    Assignee: Toko America, Inc.
    Inventor: Brian P. Erisman
  • Patent number: 5497312
    Abstract: A MOSFET driver integrated circuit or other peripheral circuit interfaced to a controller that operates on the primary side of a DC to DC converter having a high input voltage relative to the supply voltage powering both the controller and the MOSFET driver or other peripheral circuit is controlled by an under-voltage lockout circuit to transition from a standby mode to a normal operating mode of the MOSFET driver or other peripheral circuit only when the supply voltage is sufficient to sustain normal operation and the driver or other peripheral circuit senses activity at an input that indicates that the controller has previously transitioned from a standby mode to a normal operating mode.
    Type: Grant
    Filed: May 13, 1993
    Date of Patent: March 5, 1996
    Assignee: Toko America, Inc.
    Inventor: Brian P. Erisman
  • Patent number: 5402060
    Abstract: A controller for a two-switch buck-boost converter accomplishes one-at-a-time switch control by simultaneously employing an analog error signal to control one drive output and an analog inversion of that error signal, with respect to a voltage that is equal to the voltage excursion limit of a timing ramp signal, to control the other drive output. In a second embodiment of the invention, a controller employs a comparator to compare an analog error signal against a given voltage excursion limit of a timing ramp signal to perform the functions of determining which of two drive outputs is to be enabled to be modulated and of modifying the voltage excursion limits of the timing ramp signal such that the voltage excursion limit compared by the comparator is switched between two different voltage excursion limits.
    Type: Grant
    Filed: May 13, 1993
    Date of Patent: March 28, 1995
    Assignee: Toko America, Inc.
    Inventor: Brian P. Erisman