Patents by Inventor Brian T. Edgar

Brian T. Edgar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170352376
    Abstract: An implementation of a system disclosed herein provides a method for managing data streams of sequential nature, wherein the method writes the sequential chunks (fragments) directly to an open band in the order these are received from the host and includes determining an end of the incoming data write request related to streaming data and in response to the determination of the end of the incoming data write request related to streaming data, copying remaining data from a current physical band mapped to logical block addresses LBAs related to the data write requests to the allocated (open) band.
    Type: Application
    Filed: August 24, 2017
    Publication date: December 7, 2017
    Inventors: Anil Kashyap, Brian T. Edgar
  • Patent number: 9767843
    Abstract: An implementation of a system disclosed herein provides a method for managing data streams of sequential nature, wherein the method writes the sequential chunks (fragments) directly to an open band in the order these are received from the host and includes determining an end of the incoming data write request related to streaming data and in response to the determination of the end of the incoming data write request related to streaming data, copying remaining data from a current physical band mapped to logical block addresses LBAs related to the data write requests to the allocated (open) band.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: September 19, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Anil Kashyap, Brian T. Edgar
  • Publication number: 20170229145
    Abstract: An implementation of a system disclosed herein provides a method for managing data streams of sequential nature, wherein the method writes the sequential chunks (fragments) directly to an open band in the order these are received from the host and includes determining an end of the incoming data write request related to streaming data and in response to the determination of the end of the incoming data write request related to streaming data, copying remaining data from a current physical band mapped to logical block addresses LBAs related to the data write requests to the allocated (open) band.
    Type: Application
    Filed: February 5, 2016
    Publication date: August 10, 2017
    Inventors: Anil Kashyap, Brian T. Edgar
  • Publication number: 20170206161
    Abstract: A data storage device includes one or more storage media that include multiple physical storage locations. The device also includes at least one cache memory having a logical space that includes a plurality of separately managed logical block address (LBA) ranges. Additionally, a controller is included in the device. The controller is configured to receive data extents addressed by a first LBA and a logical block count. The controller is also configured to identify at least one separately managed LBA range of the plurality of separately managed LBA ranges in the at least one cache memory based on LBAs associated with at least some of the received data extents. The controller stores the at least some of the received data extents in substantially monotonically increasing LBA order in at least one physical storage location, of the at least one cache memory, assigned to the identified at least one LBA range.
    Type: Application
    Filed: April 3, 2017
    Publication date: July 20, 2017
    Inventors: Timothy R. Feldman, Andrew M. Kowles, Mark Allen Gaertner, Brian T. Edgar
  • Patent number: 9678864
    Abstract: A device includes one or more data storage media having a main storage area, and includes a non-volatile cache memory and a controller. The controller stores a plurality of data packets into a plurality of physical locations in the main storage area. Each of the data packets is associated with a different logical block address (LBA), and each of the physical locations is associated with a different physical location address (PLA). The controller generates mapping information that links the different LBAs to the different PLAs. Upon detecting a soft error when reading a data packet stored in a physical location, the controller relocates the data packet associated with the soft error to a physical location of the non-volatile cache memory. The controller also marks the physical location as a suspect location. The controller updates the mapping information to reflect the relocation of the data packet associated with the soft error.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: June 13, 2017
    Assignee: Seagate Technology LLC
    Inventors: Jun Cai, AndiSumaryo Sutiawan, Jeetandra Kella, ChuanPeng Ong, Mark Allen Gaertner, Brian T. Edgar
  • Patent number: 9612956
    Abstract: A data storage device includes one or more storage media that include multiple physical storage locations. The device also includes at least one cache memory having a logical space that includes a plurality of separately managed logical block address (LBA) ranges. Additionally, a controller is included in the device. The controller is configured to receive data extents addressed by a first LBA and a logical block count. The controller is also configured to identify at least one separately managed LBA range of the plurality of separately managed LBA ranges in the at least one cache memory based on LBAs associated with at least some of the received data extents. The controller stores the at least some of the received data extents in substantially monotonically increasing LBA order in at least one physical storage location, of the at least one cache memory, assigned to the identified at least one LBA range.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: April 4, 2017
    Assignee: Seagate Technology LLC
    Inventors: Timothy R. Feldman, Andrew M. Kowles, Mark Allen Gaertner, Brian T. Edgar
  • Patent number: 9552252
    Abstract: Certain exemplary aspects of the present disclosure are directed towards methods and apparatuses in which logic circuitry generates an error detection code based on user data received from a host, and further generates a first set of check bits, to be written to the non-volatile memory circuit in conjunction with the user data, by combining the error detection code with a hashed data address of the user data. In some embodiments, the check bits associated with the user data providing verification that the user data was written in the appropriate physical block address of the non-volatile memory circuit.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: January 24, 2017
    Assignee: Seagate Technology LLC
    Inventors: Jon D. Trantham, Brian T. Edgar, Mark Gaertner, Bruce Buch
  • Patent number: 9377956
    Abstract: Systems and methods are disclosed for performing rewrite operations on recording bands of a data storage medium. In some embodiments, a storage device may receive a write request to be recorded to a band including a plurality of contiguous data storage areas (e.g. tracks) spanning from a first storage area to a last storage area. The device may determine a target area of the band to which to record the data, and perform a partial rewrite operation on less than all data storage areas of the band when the target area is not within a threshold number of data storage areas from the first storage area. In some embodiments, the rewrite operation may include reading data recorded in a first arrangement from the target band, modifying the data, and recording the modified data to the band in a second arrangement including a physical recording order different than the first arrangement.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 28, 2016
    Assignee: Seagate Technology LLC
    Inventors: Xiong Liu, Brian T Edgar, Feng Shen, WenXiang Xie, ThanZaw Thein
  • Publication number: 20160162208
    Abstract: A device includes one or more data storage media having a main storage area. The device also includes a non-volatile cache memory and a controller. The controller stores a plurality of data packets into a plurality of physical locations in the main storage area of the one or more data storage media. Each of the plurality of data packets is associated with a different logical block address (LBA), and each of the plurality of physical locations is associated with a different physical location address. The controller generates mapping information that links the different LBAs associated with the different data packets to the different physical location addresses associated with the different physical locations.
    Type: Application
    Filed: December 3, 2014
    Publication date: June 9, 2016
    Inventors: Jun Cai, AndiSumaryo Sutiawan, Jeetandra Kella, ChuanPeng Ong, Mark Allen Gaertner, Brian T. Edgar
  • Publication number: 20160147480
    Abstract: The disclosure is related to systems and methods of managing data storage in a memory device. In a particular embodiment, a method is disclosed that includes receiving, in a data storage device, at least one data packet that has a size that is different from an allocated storage capacity of at least one physical destination location on a data storage medium in the data storage device for the at least one data packet. The method also includes storing the at least one received data packet in a non-volatile cache memory prior to transferring the at least one received data packet to the at least one physical destination location.
    Type: Application
    Filed: February 2, 2016
    Publication date: May 26, 2016
    Inventors: Luke W. Friendshuh, Brian T. Edgar, Mark A. Gaertner
  • Patent number: 9280477
    Abstract: The disclosure is related to systems and methods of managing data storage in a memory device. In a particular embodiment, a method is disclosed that includes receiving, in a data storage device, at least one data packet that has a size that is different from an allocated storage capacity of at least one physical destination location on a data storage medium in the data storage device for the at least one data packet. The method also includes storing the at least one received data packet in a non-volatile cache memory prior to transferring the at least one received data packet to the at least one physical destination location.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: March 8, 2016
    Assignee: Seagate Technology LLC
    Inventors: Luke W. Friendshuh, Brian T. Edgar, Mark A. Gaertner
  • Publication number: 20160055053
    Abstract: Certain exemplary aspects of the present disclosure are directed towards methods and apparatuses in which logic circuitry generates an error detection code based on user data received from a host, and further generates a first set of check bits, to be written to the non-volatile memory circuit in conjunction with the user data, by combining the error detection code with a hashed data address of the user data. In some embodiments, the check bits associated with the user data providing verification that the user data was written in the appropriate physical block address of the non-volatile memory circuit.
    Type: Application
    Filed: August 25, 2014
    Publication date: February 25, 2016
    Inventors: Jon D. Trantham, Brian T. Edgar, Mark Gaertner, Bruce Buch
  • Publication number: 20150301747
    Abstract: Implementations disclosed herein provide for increasing storage drive performance by reserving a region of user-writeable storage space on a storage medium for overprovisioning uses, including performance-enhancing functions. Until a capacity condition of the storage drive is satisfied, write operations targeting the reserved region are written to another equal-sized region that does not contain user data.
    Type: Application
    Filed: April 17, 2014
    Publication date: October 22, 2015
    Applicant: Seagate Technology LLC
    Inventors: Daniel J. Sokolov, Bang C. Nguyen, Andrew M. Kowles, Cameron S. McGary, Adam J. Weikal, Brian T. Edgar
  • Publication number: 20150106568
    Abstract: A data storage device includes one or more storage media that include multiple physical storage locations. The device also includes at least one cache memory having a logical space that includes a plurality of separately managed logical block address (LBA) ranges. Additionally, a controller is included in the device. The controller is configured to receive data extents addressed by a first LBA and a logical block count. The controller is also configured to identify at least one separately managed LBA range of the plurality of separately managed LBA ranges in the at least one cache memory based on LBAs associated with at least some of the received data extents. The controller stores the at least some of the received data extents in substantially monotonically increasing LBA order in at least one physical storage location, of the at least one cache memory, assigned to the identified at least one LBA range.
    Type: Application
    Filed: December 18, 2014
    Publication date: April 16, 2015
    Inventors: Timothy R. Feldman, Andrew M. Kowles, Mark Allen Gaertner, Brian T. Edgar
  • Patent number: 9007710
    Abstract: Systems and methods are disclosed for performing a rewrite operation on recording bands of a data storage medium. In some embodiments, data may be read from a target band including a plurality of tracks, and modified. A portion less than all of the modified data is stored to a nonvolatile memory, and all of the modified data is written to the target band. In some embodiments, modified data corresponding to the first two tracks of the target band is stored to the nonvolatile memory, and modified data corresponding to the third track of the target band is written back to the first physical track. Each track may be written in order, ending with the modified data corresponding to the first two tracks. The result may be that data for each track in the band has shifted up two tracks, with data for the first two tracks moved to the end.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: April 14, 2015
    Assignee: Seagate Technology
    Inventors: Xiong Liu, Brian T Edgar, Feng Shen, WenXiang Xie, ThanZaw Thein
  • Patent number: 8694970
    Abstract: A unified debug system with multiple user-configurable trace volumes is disclosed, including embodiments as a system, a method, and a computer-readable medium. Embodiments of the present invention provide more robust and flexible solutions for introducing configurable trace volumes to firmware, allowing a user to specify firmware system configurations for trace buffers, trace frames, and trace volumes, and offer other advantages over the prior art. One embodiment of the present invention pertains to a system that includes a firmware component comprising firmware, and a firmware interface communicatively connected to the firmware component. The firmware includes a plurality of trace volumes for storing a plurality of trace entries. The trace volumes are user-configurable through the firmware interface. The plurality of trace volumes includes first, second and third trace volumes. The first trace volume includes storing at least some of the trace entries to a trace buffer in a first volatile memory component.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: April 8, 2014
    Assignee: Seagate Technology LLC
    Inventors: Brian T. Edgar, Mark A. Gaertner, Bhooshan S. Thakar
  • Publication number: 20120151134
    Abstract: The disclosure is related to systems and methods of managing data storage in a memory device. In a particular embodiment, a method is disclosed that includes receiving, in a data storage device, at least one data packet that has a size that is different from an allocated storage capacity of at least one physical destination location on a data storage medium in the data storage device for the at least one data packet. The method also includes storing the at least one received data packet in a non-volatile cache memory prior to transferring the at least one received data packet to the at least one physical destination location.
    Type: Application
    Filed: November 9, 2011
    Publication date: June 14, 2012
    Applicant: Seagate Technology LLC
    Inventors: Luke W. Friendshuh, Brian T. Edgar, Mark A. Gaertner
  • Patent number: 7406628
    Abstract: A method and device are provided that use a sequencer in the device to control interactions on an interface bus. The sequencer is programmed to interrupt a co-processor before execution of a command. Based on the interrupt signal and a stored error mode page, a false error condition is initiated by further programming the sequencer to operate abnormally. After recovery from the error condition, the sequencer is reprogrammed to operate normally.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: July 29, 2008
    Assignee: Seagate Technology LLC
    Inventors: Brian T. Edgar, Feng Li, Mark A. Schmidt
  • Patent number: 6286056
    Abstract: A disc drive includes a disc which is coupled to a spindle motor for rotation. A head in the disc drive is configured to read and write data upon the disc. The disc drive also includes a controller which is couplable to an SCSI interface, and adapted to store persistent reservation information on the disc. Methods are also provided by which SCSI compliant devices can respond to persistent reservations commands in accordance with the present invention.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: September 4, 2001
    Assignee: Seagate Technology LLC
    Inventors: Brian T. Edgar, Gerald A. Houlder