Patents by Inventor Bruce Del Signore

Bruce Del Signore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10177781
    Abstract: A method includes selectively coupling first and second input nodes of a capacitive bridge to first and second voltages, respectively, and selectively coupling first and second output nodes of the capacitive bridge to first and second output terminals, respectively, during a first phase of a clock cycle. The method further includes selectively coupling the first and second input nodes to the second and first voltages, respectively, and selectively coupling the first and second output nodes to the second and first output terminals, respectively, during a second phase of the clock cycle.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: January 8, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Louis Nervegna, Bruce Del Signore
  • Publication number: 20170194854
    Abstract: A DC-DC converter includes a plurality of switches configured to be in a first charging mode until current through an inductor reaches a first current threshold to thereby indicate an end of the first charging mode. Responsive to the end of the first charging mode the DC-DC converter is configured to operate in a second charging mode for a time period ?T in which a first side of the inductor is coupled to an input voltage and a second side of the inductor is coupled to a load. Responsive to the end of the time period ?T, the DC-DC converter operates in a discharge mode until current through the inductor reaches its minimum.
    Type: Application
    Filed: December 30, 2015
    Publication date: July 6, 2017
    Inventors: Alexander Cherkassky, Bruce Del Signore
  • Patent number: 9698674
    Abstract: A DC-DC converter includes a plurality of switches configured to be in a first charging mode until current through an inductor reaches a first current threshold to thereby indicate an end of the first charging mode. Responsive to the end of the first charging mode the DC-DC converter is configured to operate in a second charging mode for a time period ?T in which a first side of the inductor is coupled to an input voltage and a second side of the inductor is coupled to a load. Responsive to the end of the time period ?T, the DC-DC converter operates in a discharge mode until current through the inductor reaches its minimum.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: July 4, 2017
    Assignee: Silicon Laboratories Inc.
    Inventors: Alexander Cherkassky, Bruce Del Signore
  • Patent number: 9157937
    Abstract: An integrator circuit includes a switched capacitor bridge including first and second inputs and first and second outputs. The switched capacitor bridge is configured to sample first and second reference voltages twice per unit time interval. The integrator circuit further includes an integrator coupled to the first and second outputs and configured to integrate charge dumped into the first and second outputs twice per unit time interval.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: October 13, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: Louis Nervegna, Bruce Del Signore
  • Publication number: 20140375135
    Abstract: A method includes selectively coupling first and second input nodes of a capacitive bridge to first and second voltages, respectively, and selectively coupling first and second output nodes of the capacitive bridge to first and second output terminals, respectively, during a first phase of a clock cycle. The method further includes selectively coupling the first and second input nodes to the second and first voltages, respectively, and selectively coupling the first and second output nodes to the second and first output terminals, respectively, during a second phase of the clock cycle.
    Type: Application
    Filed: June 24, 2013
    Publication date: December 25, 2014
    Inventors: Louis Nervegna, Bruce Del Signore
  • Publication number: 20140375374
    Abstract: An integrator circuit includes a switched capacitor bridge including first and second inputs and first and second outputs. The switched capacitor bridge is configured to sample first and second reference voltages twice per unit time interval. The integrator circuit further includes an integrator coupled to the first and second outputs and configured to integrate charge dumped into the first and second outputs twice per unit time interval.
    Type: Application
    Filed: July 30, 2013
    Publication date: December 25, 2014
    Applicant: Silicon Laboratories Inc.
    Inventors: Louis Nervegna, Bruce Del Signore
  • Patent number: 7746262
    Abstract: A method for coding a digital to analog converter of a successive approximation register analog to digital converter includes the steps of first switching capacitors associated with a bit from ground to a reference voltage. Next, a determination is made of whether a logical value of the bit is a first or a second value. If the logical value is the first value, capacitors associated with a next bit are switched from ground to a reference voltage. If the logical value is the second value, one half of the capacitors associated with the bit currently connected are switched from the reference voltage to ground.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: June 29, 2010
    Assignee: Silicon Laboratories Inc.
    Inventors: Golam R. Chowdhury, Douglas S. Piasecki, Bruce Del Signore, Kevin Kwak
  • Publication number: 20070139243
    Abstract: A method for coding a digital to analog converter of a successive approximation register analog to digital converter includes the steps of first switching capacitors associated with a bit from ground to a reference voltage. Next, a determination is made of whether a logical value of the bit is a first or a second value. If the logical value is the first value, capacitors associated with a next bit are switched from ground to a reference voltage. If the logical value is the second value, one half of the capacitors associated with the bit currently connected are switched from the reference voltage to ground.
    Type: Application
    Filed: December 19, 2005
    Publication date: June 21, 2007
    Applicant: SILICON LABORATORIES, INC.
    Inventors: Golam R. Chowdhury, Douglas S. Piasecki, Kevin Kwak, Bruce Del Signore
  • Patent number: 7113009
    Abstract: A divider is disclosed herein. The divider includes a sequence of divide stages programmably coupled to provide a variety of divide ratios. The divider also includes one or more multiplexers to feedback the output of a divide stage to the input of a divide stage earlier in the sequence of divide stages. The divider may also include duty cycle correction circuitry and self correction logic to correct abnormal logic states. The divide stages can operate in synchronism with each other. Multiplexer functionality, self correction circuitry functionality, and divide stage functionality may be implemented in a combination latch circuit.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: September 26, 2006
    Assignee: Silicon Laboratories Inc.
    Inventors: Lizhong Sun, Bruce Del Signore, Axel Thomsen, Douglas F. Pastorello
  • Publication number: 20050285629
    Abstract: An output buffer circuit drives multiple signal formats. The output buffer circuit reduces duplication of output bond pads on an integrated circuit die. The output buffer circuit reduces a need for including conversion buffers on system boards. A single integrated circuit including the output buffer circuit may meet a variety of applications. The output buffer achieves these results with a programmable output voltage swing and a programmable output common mode voltage. In some embodiments of the present invention, an integrated circuit includes at least one single-ended buffer and at least one differential circuit coupled to a pair of outputs. One of the single-ended buffer and the differential circuit is selectively enabled to provide a signal to the outputs.
    Type: Application
    Filed: June 28, 2004
    Publication date: December 29, 2005
    Inventors: Jerrell Hein, Bruce Del Signore, Akhil Garlapati
  • Publication number: 20050285666
    Abstract: A voltage reference generator generates a stable reference voltage that is less than the bandgap voltage of silicon for power supply voltages less than 2V, yet provides sufficient voltage headroom to operate a current mirror. In one embodiment, the voltage reference generator has a power supply rejection ratio of at least 60 dB and has comparable noise performance as compared to traditional bandgap cirucits. These advantages are achieved by subtracting a current proportional to a complement of an absolute temperature from a current proportional to the absolute temperature to generate a voltage having a positive temperature coefficient, which is then added to a voltage that is a complement of the absolute temperature to achieve a voltage that has a low temperature coefficient.
    Type: Application
    Filed: June 25, 2004
    Publication date: December 29, 2005
    Inventors: Akhil Garlapati, David Pietruszynski, Bruce Del Signore
  • Publication number: 20050218879
    Abstract: A voltage reference generator has been discovered that generates a stable reference voltage that is less than the bandgap voltage of silicon for power supply voltages less than 2V, yet provides sufficient voltage headroom to operate a cascaded current mirror. In one embodiment, the voltage reference generator has a power supply rejection ratio of at least 60 dB and has improved noise performance as compared to traditional bandgap circuits. These advantages are achieved by leveraging the low-beta effect of a CMOS bipolar transistor to generate a current proportional to an absolute temperature.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 6, 2005
    Inventors: Akhil Garlapati, Bruce Del Signore, David Pietruszynski
  • Patent number: 6002355
    Abstract: An analog-to-digital converter (ADC) architecture is fabricated on a semiconductor substrate which is negatively capacitively charge pumped below ground and subject to feedback regulation, rate measurements and adjustments. The ADC receives signal inputs of positive and negative polarity relative to ground, while being powered at 0V and 5V, without any negative power source input, as a result of a closed feedback loop which keeps the negative bias voltage constant as external supplies and component voltages vary. The high frequency pumping of the silicon substrate is subject to timing requirements which permit high resolution analog input signals to be converted in the presence of pump noise.
    Type: Grant
    Filed: June 26, 1997
    Date of Patent: December 14, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: Bruce Del Signore, Qicheng Yu, Jerome E. Johnston
  • Patent number: 5157395
    Abstract: An analog-to-digital converter includes a delta-sigma modulator (10), having the output thereof filtered by a digital filter section. The digital filter section includes a first fixed decimation filter (12) followed by a variable decimation filter section (14) and an output low-pass filter section (16), having a fixed decimation ratio. The fixed variable decimation filter section (14) includes a single FIR filter (24) that has data processed therethrough with different sampling rates. A recursive controller (26) receives an external configuration input to determine the number of passes through the filter (24) that are required to provide the desired decimation ratio.
    Type: Grant
    Filed: March 4, 1991
    Date of Patent: October 20, 1992
    Assignee: Crystal Semiconductor Corporation
    Inventors: Bruce Del Signore, Eric J. Swanson, Jeffrey M. Klaas, David L. Medlock