Abstract: An exemplary data refresh method disclosed herein reading data into volatile memory from a first storage region using a read element controlled by a first actuator assembly and writing the data from the volatile memory to a second storage region using a write element controlled by a second actuator assembly, where the first actuator assembly and the second actuator assembly are configured to receive data from control circuitry via independent read/write communication channels.

Abstract: A data storage device includes a first system-on-a-chip (SOC) associated with a first read transducer that accesses one or more magnetic disks of the data storage drive. The first SOC has a first read channel operable to receive data from the first read transducer. A second SOC is associated with a second read transducer that accesses the one or more magnetic disks of the data storage drive independently of the first read transducer. The second SOC has a second read channel operable to receive second data from the second read transducer. The first and second SOCs are coupled via a data bus that facilitates communicating the first and second data to a host via a first host interface.

Abstract: An apparatus comprises a plurality of servo controllers and a plurality of motor control circuits. Each of the plurality of motor control circuits has a primary serial interface (SIF) coupled to one of the plurality of servo controllers and at least one secondary SIF coupled to others of the plurality of servo controllers. Each of a plurality of independently controllable actuators is coupled to one of the motor control circuits. Each of the plurality of motor control circuits is configured to generate a compensated control signal using an actuator command received from the primary SIF and an actuator command received from the at least one secondary SIF. Each of the plurality of motor control circuits is configured to control movement of one of the plurality of actuators using the compensated control signal.

Abstract: An exemplary data refresh method disclosed herein reading data into volatile memory from a first storage region using a read element controlled by a first actuator assembly and writing the data from the volatile memory to a second storage region using a write element controlled by a second actuator assembly, where the first actuator assembly and the second actuator assembly are configured to receive data from control circuitry via independent read/write communication channels.

Abstract: An exemplary data refresh method disclosed herein reading data into volatile memory from a first storage region using a read element controlled by a first actuator assembly and writing the data from the volatile memory to a second storage region using a write element controlled by a second actuator assembly, where the first actuator assembly and the second actuator assembly are configured to receive data from control circuitry via independent read/write communication channels.

Abstract: A chip configured with pin-strapping includes a configuration pin coupled to a resistor, the resistor coupled a configuration circuit configured to provide a threshold voltage at a sense time interval. A configuration vector may be determined by driving the configuration pin with high impedance, and sampling the configuration pin at sense time intervals such that the configuration vector corresponds to the time interval at which a threshold voltage is reached.

Abstract: One or more magnetic recording disks are coupled to a spindle motor, each of the disks having opposing recording surfaces. Two or more actuators are moveable independently over at least a first recording surface of the one or more disks. A first actuator of the two or more actuators comprises a first write head and a first read head. A second actuator of the two or more actuators comprises at least a second read head and may include a second write head. A controller is coupled to the two or more actuators and configured to write data to a track on the first recording surface using the first write head, and perform a read operation on the data written to the track using the second read head. The controller is also configured to verify that the data was successfully written to the track in response to the read operation. The read operation can be performed within less than one revolution of the first recording surface after the write operation.

Abstract: In certain embodiments, an apparatus may comprise a first output driver connected to a first output via a first trace and a second output driver connected to a second output via a second trace. The first output driver may be configured to output a first drive signal to the first output to drive the first output and the first drive signal may cause first induced noise in the second trace. Further, the second output driver may be configured to output a second drive signal based on the first drive signal where the second drive signal may reduce the magnitude of the first induced noise at the second output.

Abstract: One or more detectors detect data from respective one or more analog sources operable to read from a storage medium. A buffer pool is between the decoders and two or more detectors. The decoders are simultaneously operable, via the buffer pool, to independently decode the data from the one or more detectors.

Abstract: Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from the generated data.

Abstract: A data storage device includes first and second controllers that independently and simultaneously process data from a recording medium. The first and second controllers each have respective first and second buffer managers coupled to respective first and second buffer memories. The first and second buffer managers are coupled to each other via an inter-controller data bus. The first controller is configured to receive a contiguous memory request for a block data transfer client of the first controller. A first part of the request is fulfilled from the first buffer memory via the first buffer manager, and a second part of the request is fulfilled from the second buffer memory via the second buffer manager communicating with the first buffer manager via the inter-controller data bus.

Abstract: In a device with first and second heads, the second head is held at a radial location over one or more disks via a second actuator that moves the second head. A position error of the second head is read while performing a seek with a first actuator, the first actuator moving the first head over the one or more disks. A mechanical transfer function is determined between the first actuator and the second actuator based on the position error of the second head. The mechanical transfer function is used to provide compensation for the second head via the second actuator in response to subsequent seek of the first actuator.

Abstract: One or more magnetic recording disks are coupled to a spindle motor, each of the disks having opposing recording surfaces. Two or more actuators are moveable independently over at least a first recording surface of the one or more disks. A first actuator of the two or more actuators comprises a first write head and a first read head. A second actuator of the two or more actuators comprises at least a second read head and may include a second write head. A controller is coupled to the two or more actuators and configured to write data to a track on the first recording surface using the first write head, and perform a read operation on the data written to the track using the second read head. The controller is also configured to verify that the data was successfully written to the track in response to the read operation. The read operation can be performed within less than one revolution of the first recording surface after the write operation.

Abstract: Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from the generated data.

Abstract: First and second servo control processors are coupled to respective first and second actuators that independently position first and second heads over one or more disks of a data storage drive. The first and second servo control processors are further coupled to first and second low-latency ports. First and second unidirectional buses couple the first and second low-latency ports. The first and second unidirectional busses are operable to isochronously exchange servo positioning data between the first and second servo control processors. The first and second servo control processors each use the servo positioning data to compensate for movement caused by another of the first and second servo control processors.

Abstract: In certain embodiments, an apparatus may comprise a first output driver connected to a first output via a first trace and a second output driver connected to a second output via a second trace. The first output driver may be configured to output a first drive signal to the first output to drive the first output and the first drive signal may cause first induced noise in the second trace. Further, the second output driver may be configured to output a second drive signal based on the first drive signal where the second drive signal may reduce the magnitude of the first induced noise at the second output.

Abstract: A system includes a memory, a processor, an encoder, a head, and a decoder. The memory stores information. The processor processes information and controls operation of other components. The encoder encodes a first portion and a second portion of a servo track to form a first and second encoded values. The second code has a run length associated therewith. The first and second encoded values result in a Gray code. Each bit of the Gray code remains constant for at least a number of tracks corresponding to the run length. The head is configured to write the first and the second encoded values onto a media, and is configured to read the first and the second encoded values from the media. The decoder decodes the first encoded value and the second encoded value. The processor determines a servo track address from the decoded first value and the decoded second value.

Abstract: An apparatus comprises a recording transducer configured for microwave-assisted magnetic recording (MAMR) and a magnetic recording medium. The recording transducer comprises a write pole configured to generate a write magnetic field and a write-assist arrangement proximate the write pole. The write-assist arrangement is configured to generate a radio frequency assist magnetic field at a plurality of different frequencies. The magnetic recording medium comprises a plurality of tracks, wherein adjacent tracks of the medium have different ferromagnetic resonant frequencies.

Abstract: A recording head is configured to write and read data sectors to and from a recording medium, such as a heat-assisted recording medium. A read channel is coupled to the recording head. Phase-locked loop (PLL) circuitry of the read channel is configured to detect a change in a phase error at a location of the data sector. The phase error change may be indicative of a mode-hop that occurred while writing the data sector to the medium. The PLL circuitry is configured to determine a phase offset using the phase error. A controller is configured to effect re-reading of the data sector location using the phase offset to recover the data sector location.

Abstract: A recording head is configured to write and read data sectors to and from a recording medium, such as a heat-assisted recording medium. A read channel is coupled to the recording head. Phase-locked loop (PLL) circuitry of the read channel is configured to detect a change in a phase error at a location of the data sector. The phase error change may be indicative of a mode-hop that occurred while writing the data sector to the medium. The PLL circuitry is configured to determine a phase offset using the phase error. A controller is configured to effect re-reading of the data sector location using the phase offset to recover the data sector location.