Abstract: A memory includes a first memory cell; and a second memory cell. A selectable current path is coupled between the first memory cell and the second memory cell. The selectable current path includes a first transistor. A first amplifier is coupled in a first feedback arrangement between the first memory cell and the first transistor. During a read operation of the first memory cell, a current through the first memory cell is substantially equal to a current through the second memory cell. The memory cell may include a magnetic tunnel junction (MTJ).

Abstract: A memory includes a first memory cell; and a second memory cell. A selectable current path is coupled between the first memory cell and the second memory cell. The selectable current path includes a first transistor. A first amplifier is coupled in a first feedback arrangement between the first memory cell and the first transistor. During a read operation of the first memory cell, a current through the first memory cell is substantially equal to a current through the second memory cell. The memory cell may include a magnetic tunnel junction (MTJ).

Abstract: A memory includes a first memory cell; and a second memory cell. A selectable current path is coupled between the first memory cell and the second memory cell. The selectable current path includes a first transistor. A first amplifier is coupled in a first feedback arrangement between the first memory cell and the first transistor. During a read operation of the first memory cell, a current through the first memory cell is substantially equal to a current through the second memory cell. The memory cell may include a magnetic tunnel junction (MTJ).

Abstract: A memory includes a first memory cell; and a second memory cell. A selectable current path is coupled between the first memory cell and the second memory cell. The selectable current path includes a first transistor. A first amplifier is coupled in a first feedback arrangement between the first memory cell and the first transistor. During a read operation of the first memory cell, a current through the first memory cell is substantially equal to a current through the second memory cell. The memory cell may include a magnetic tunnel junction (MTJ).

Abstract: A memory device includes a first memory cell having a first transistor, a second transistor, and a resistive storage element. During a read operation, sense current is conducted through the second transistor and the first transistor is used to sense feedback voltage at a first terminal of the resistive storage element. During a write operation, current is conducted through the first and second transistors.

Abstract: A data processing system (10) has an embedded non-volatile memory (22) that is programmed and erased by use of a high voltage provided by a charge pump (78). In order to prevent the non-volatile memory (22) from being inadvertently programmed or erased during low power supply voltage conditions, the charge pump (78) is disabled and discharged when the power supply voltage drops below a predetermined value. This is accomplished by enabling a low voltage detect circuit (110) in response to a program or erase operation being initiated. A control register (76) will provide a high voltage enable signal to the charge pump (78) only when a power supply valid signal is received. In another embodiment, the low voltage detect circuit (110) may be enabled by another condition to protect the data processing system (10) from an authorized access.

Abstract: A single memory array (10) has an isolation circuit for isolating segments of a same bit line (Seg1 BL0, Seg2 BL0) from each other. The isolation circuit (16) permits memory cells located in one segment (12) of an array to be read while memory cells of another segment (14) of the array are being erased. In one example, the isolation circuit (16) electrically couples the segments during a read or program of memory cells located on the second segment (Seg2 BL0). Program information stored in the single memory array may always be accessed while a portion of the same array is erased. Dynamic variation of the size of the isolated bit line segment occurs when multiple isolation circuits are used to create more than two array segments.

Abstract: A memory array of one-transistor (1T) SONOS bit cells in a common-source architecture is used in conjunction with a reverse read technique to reduce the effect of read disturb. Bit line voltage in the array, during read operation, is constrained to a Vt or less, relative to the control gate, so that read disturb is limited. When information is programmed into a bit cell in the array, the bit line is used as a drain, which has the effect of concentrating charge toward the bitline end of the SONOS transistor. When information is read from a bit cell in the array, the bit line of the selected bit cell is used as a source, instead of a drain. That reversal gives a larger Vt contrast between a 0 and a 1 than a forward read, for a given amount of stored charge.

Abstract: A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.

Abstract: A memory device is disclosed having a column select transistor gate that is controlled by tri-statable control logic. The tri-statable control logic operates to allow the gate of the column select transistor to float during sensing of the bit cell. The column select transistor acts as a floating gate amplifier, i.e. a common gate amplifier having a gate that floats during the sensing period. In addition, the column select transistor can operate to facilitate decoding of the memory and to allow precharge of a bit line of a memory cell. Further, avoidance of a static power drain is made possible by the fact that the gate is floating during the sensing period.

Abstract: A memory device is disclosed having a column select transistor gate that is controlled by tri-statable control logic. The tri-statable control logic operates to allow the gate of the column select transistor to float during sensing of the bit cell. The column select transistor acts as a floating gate amplifier, i.e. a common gate amplifier having a gate that floats during the sensing period. In addition, the column select transistor can operate to facilitate decoding of the memory and to allow precharge of a bit line of a memory cell. Further, avoidance of a static power drain is made possible by the fact that the gate is floating during the sensing period.

Abstract: A memory array of one-transistor (1T) SONOS bit cells in a common-source architecture is used in conjunction with a reverse read technique to reduce the effect of read disturb. Bit line voltage in the array, during read operation, is constrained to a Vt or less, relative to the control gate, so that read disturb is limited. When information is programmed into a bit cell in the array, the bit line is used as a drain, which has the effect of concentrating charge toward the bitline end of the SONOS transistor. When information is read from a bit cell in the array, the bit line of the selected bit cell is used as a source, instead of a drain. That reversal gives a larger Vt contrast between a 0 and a 1 than a forward read, for a given amount of stored charge.

Abstract: A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.

Abstract: A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide “1” outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide “0” outputs from selected cells.

Abstract: A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines a connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide “1” outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide “0” outputs from selected cells.

Abstract: A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines, one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide “1” outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide “0” outputs from selected cells.

Abstract: A method and apparatus for performing mis-aligned read and write operations to a stack involves providing a memory array (110). The memory array is split into a high byte memory array (116) and a low byte memory array (112). Each memory array (112 and 116) has its own bus interface unit (114 and 118) respectively. The high byte bus interface unit (118) increments the address bits to the high byte memory array (116) on every access to compensate for mis-aligned data. However, the low byte bus interface unit (114) does not increment the address value before accessing the memory array (112). By doing so, memory is read from the memory arrays (112 and 116) in either 8 bit sizes or 16 bit sizes regardless of whether the stack structure implemented in memory array (112 and/or 116) contains aligned data or mis-aligned data.

Abstract: A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.

Abstract: A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.

Abstract: A non-linear charge pump (1120) provides various voltages for use in a nonvolatile memory (400) and operates at low power supply voltages. The non-linear charge pump (1120) includes at least two non-linear voltage doubling stages (1132, 1134), which allows a capacitor formed with relatively thin gate oxide in a first stage (1132) to be made larger than a capacitor formed using relatively thick gate oxide in a second stage (1134). An output of a last voltage doubling stage (1136) is then input to a linear stage (1150) to generate a precise voltage. Another charge pump (1140) including non-linear stages (1142, 1144) followed by a linear stage (1146) is used to generate a reference voltage for the main non-linear charge pump (1130). The nonlinear stage (1130) includes a special bulk biasing circuit to bias the bulk of a transistor (1285) on the output side of the charging circuit (1284, 1285, 1286, 1287) continuously to prevent forward biasing the parasitic drain-bulk diode.