Patents by Inventor Bruce M. Green

Bruce M. Green has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10825924
    Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The gate may be configured to include a lateral overhang that is separated from an upper surface of the first dielectric layer.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: November 3, 2020
    Assignee: NXP USA, Inc.
    Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
  • Patent number: 10541324
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate, a buffer layer that includes at least one additional layer formed over the substrate, a channel layer formed over the buffer layer, a barrier layer formed over the channel layer forming a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and an ohmic contact recessed into the barrier layer. A method for fabricating the semiconductor device includes forming a semiconductor substrate that includes a mixed crystal layer, creating an isolation region that defines an active region along an upper surface of the semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and recessing an ohmic contact into the semiconductor substrate.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: January 21, 2020
    Assignee: NXP USA, Inc.
    Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
  • Patent number: 10522670
    Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: December 31, 2019
    Assignee: NXP USA, Inc.
    Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
  • Patent number: 10249615
    Abstract: A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: April 2, 2019
    Assignee: NXP USA, INC.
    Inventors: Bruce M. Green, James A. Teplik
  • Patent number: 10074588
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: September 11, 2018
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Bruce M. Green, Darrell G. Hill, L. M. Mahalingam
  • Patent number: 10033374
    Abstract: An embodiment of a device includes a terminal, an active transistor die electrically coupled to the terminal, a detector configured to sense a signal characteristic on the terminal, and control circuitry electrically coupled to the active transistor die and to the detector, wherein the active transistor die, detector, and control circuitry are coupled to a package. The control circuitry may include a control element and a control device. Based on the signal characteristic, the control circuitry controls which of multiple operating states the device operates. A method for controlling the operating state of the device includes sensing, using the detector, a signal characteristic at the terminal, and determining, using the control device, whether the signal characteristic conforms to a pre-set criteria, and when the signal characteristic does not conform to the pre-set criteria, modifying the state of the control element to alter the operating state of the device.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: July 24, 2018
    Assignee: NXP USA, INC.
    Inventors: Bruce M. Green, Enver Krvavac, Joseph Staudinger
  • Patent number: 9871107
    Abstract: An embodiment of a device includes a semiconductor substrate, a transistor formed at the first substrate surface, a first conductive feature formed over the first substrate surface and electrically coupled to the transistor, and a second conductive feature covering only a portion of the second substrate surface to define a first conductor-less region. A cavity vertically aligned with the first conductive feature within the first conductor-less region extends into the semiconductor substrate. A dielectric medium may be disposed within the cavity and have a dielectric constant less than a dielectric constant of the semiconductor substrate. A method for forming the device may include forming a semiconductor substrate, forming a transistor on the semiconductor substrate, forming the first conductive feature, forming the second conductive feature, forming the conductor-less region, forming the cavity, and filling the cavity with the dielectric medium.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: January 16, 2018
    Assignee: NXP USA, INC.
    Inventors: Bruce M. Green, Jenn Hwa Huang, Vikas S. Shilimkar
  • Publication number: 20170317202
    Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The gate may be configured to include a lateral overhang that is separated from an upper surface of the first dielectric layer.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
  • Patent number: 9799760
    Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: October 24, 2017
    Assignee: NXP USA, INC.
    Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
  • Publication number: 20170294531
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a Schottky metal layer disposed over the substrate adjacent the gate electrode. The Schottky metal layer includes a Schottky contact electrically coupled to the channel which provides a Schottky junction and at least one alignment mark disposed over the semiconductor substrate. A method for fabricating the semiconductor device includes creating an isolation region that defines an active region along an upper surface of a semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and forming a Schottky metal layer over the semiconductor substrate. Forming the Schottky metal layer includes forming at least one Schottky contact electrically coupled to the channel and providing a Schottky junction, and forming an alignment mark in the isolation region.
    Type: Application
    Filed: June 19, 2017
    Publication date: October 12, 2017
    Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
  • Publication number: 20170257091
    Abstract: An embodiment of a device includes a terminal, an active transistor die electrically coupled to the terminal, a detector configured to sense a signal characteristic on the terminal, and control circuitry electrically coupled to the active transistor die and to the detector, wherein the active transistor die, detector, and control circuitry are coupled to a package. The control circuitry may include a control element and a control device. Based on the signal characteristic, the control circuitry controls which of multiple operating states the device operates. A method for controlling the operating state of the device includes sensing, using the detector, a signal characteristic at the terminal, and determining, using the control device, whether the signal characteristic conforms to a pre-set criteria, and when the signal characteristic does not conform to the pre-set criteria, modifying the state of the control element to alter the operating state of the device.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 7, 2017
    Inventors: Bruce M. Green, Enver Krvavac, Joseph Staudinger
  • Publication number: 20170236929
    Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.
    Type: Application
    Filed: May 4, 2017
    Publication date: August 17, 2017
    Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
  • Publication number: 20170207142
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.
    Type: Application
    Filed: April 3, 2017
    Publication date: July 20, 2017
    Inventors: Lakshminarayan Viswanathan, Bruce M. Green, Darrell G. Hill, L. M. Mahalingam
  • Patent number: 9685345
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a Schottky metal layer disposed over the substrate adjacent the gate electrode. The Schottky metal layer includes a Schottky contact electrically coupled to the channel which provides a Schottky junction and at least one alignment mark disposed over the semiconductor substrate. A method for fabricating the semiconductor device includes creating an isolation region that defines an active region along an upper surface of a semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and forming a Schottky metal layer over the semiconductor substrate. Forming the Schottky metal layer includes forming at least one Schottky contact electrically coupled to the channel and providing a Schottky junction, and forming an alignment mark in the isolation region.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: June 20, 2017
    Assignee: NXP USA, INC.
    Inventors: Bruce M. Green, Darrell G. Hill, Karen E. Moore
  • Patent number: 9660641
    Abstract: An embodiment of a device includes a terminal, an active transistor die electrically coupled to the terminal, a detector configured to sense a signal characteristic on the terminal, and control circuitry electrically coupled to the active transistor die and to the detector, wherein the active transistor die, detector, and control circuitry are coupled to a package. The control circuitry may include a control element and a control device. Based on the signal characteristic, the control circuitry controls which of multiple operating states the device operates. A method for controlling the operating state of the device includes sensing, using the detector, a signal characteristic at the terminal, and determining, using the control device, whether the signal characteristic conforms to a pre-set criteria, and when the signal characteristic does not conform to the pre-set criteria, modifying the state of the control element to alter the operating state of the device.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: May 23, 2017
    Assignee: NXP USA, INC.
    Inventors: Bruce M. Green, Enver Krvavac, Joseph Staudinger
  • Patent number: 9614046
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: April 4, 2017
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Bruce M. Green, Darrell G. Hill, L. M. Mahalingam
  • Publication number: 20160380626
    Abstract: An embodiment of a device includes a terminal, an active transistor die electrically coupled to the terminal, a detector configured to sense a signal characteristic on the terminal, and control circuitry electrically coupled to the active transistor die and to the detector, wherein the active transistor die, detector, and control circuitry are coupled to a package. The control circuitry may include a control element and a control device. Based on the signal characteristic, the control circuitry controls which of multiple operating states the device operates. A method for controlling the operating state of the device includes sensing, using the detector, a signal characteristic at the terminal, and determining, using the control device, whether the signal characteristic conforms to a pre-set criteria, and when the signal characteristic does not conform to the pre-set criteria, modifying the state of the control element to alter the operating state of the device.
    Type: Application
    Filed: August 5, 2016
    Publication date: December 29, 2016
    Inventors: BRUCE M. GREEN, ENVER KRVAVAC, JOSEPH STAUDINGER
  • Publication number: 20160343809
    Abstract: An embodiment of a device includes a semiconductor substrate, a transistor formed at the first substrate surface, a first conductive feature formed over the first substrate surface and electrically coupled to the transistor, and a second conductive feature covering only a portion of the second substrate surface to define a first conductor-less region. A cavity vertically aligned with the first conductive feature within the first conductor-less region extends into the semiconductor substrate. A dielectric medium may be disposed within the cavity and have a dielectric constant less than a dielectric constant of the semiconductor substrate. A method for forming the device may include forming a semiconductor substrate, forming a transistor on the semiconductor substrate, forming the first conductive feature, forming the second conductive feature, forming the conductor-less region, forming the cavity, and filling the cavity with the dielectric medium.
    Type: Application
    Filed: May 22, 2015
    Publication date: November 24, 2016
    Inventors: BRUCE M. GREEN, JENN HWA HUANG, VIKAS S. SHILIMKAR
  • Publication number: 20160308010
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.
    Type: Application
    Filed: June 3, 2016
    Publication date: October 20, 2016
    Inventors: Lakshminarayan Viswanathan, Bruce M. Green, Darrell G. Hill, L. M. Mahalingam
  • Patent number: 9438224
    Abstract: An embodiment of a device includes a terminal, an active transistor die electrically coupled to the terminal, a detector configured to sense a signal characteristic on the terminal, and control circuitry electrically coupled to the active transistor die and to the detector, wherein the active transistor die, detector, and control circuitry are coupled to a package. The control circuitry may include a control element and a control device. Based on the signal characteristic, the control circuitry controls which of multiple operating states the device operates. A method for controlling the operating state of the device includes sensing, using the detector, a signal characteristic at the terminal, and determining, using the control device, whether the signal characteristic conforms to a pre-set criteria, and when the signal characteristic does not conform to the pre-set criteria, modifying the state of the control element to alter the operating state of the device.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: September 6, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Bruce M. Green, Enver Krvavac, Joseph Staudinger