Patents by Inventor Bruno A. Mattedi

Bruno A. Mattedi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4589067
    Abstract: A full floating point vector processor includes a master processing unit having DMA I/O means, a wide bandwidth data memory having static RAM and/or interleaved dynamic RAM, an address generator operative to provide address generation for data loaded in the data memory, a concurrently operating pipeline control sequencer operative to provide fully programmable horizontal format microinstructions synchronously with the addresses generated by the address generator, and a pipelined arithmetic and logical unit responsive to the addressed data and to the synchronously provided microinstructions and operative to evaluate one of a user selectable plurality of computationally intensive functions. The address generator, the pipeline controlsequencer, and the master processing unit are configured in parallel. The address generator includes means operative to provide pipeline input and output data dependent address generation.
    Type: Grant
    Filed: May 27, 1983
    Date of Patent: May 13, 1986
    Assignee: Analogic Corporation
    Inventors: John B. Porter, David W. Altmann, Bruno A. Mattedi, Ralph Jones
  • Patent number: 4562553
    Abstract: A floating point arithmetic system with rounding anticipation including an arithmetic unit for arithmetically combining two mantissas; a carry circuit for determining whether the sum will overflow upon the addition of two mantissas and whether the difference will have a leading zero upon the subtraction of two mantissas; the subtrahend in subtraction and the augend in addition include guard, round, and sticky digits; a rounding circuit is responsive to the carry circuit for rounding the least significant digit of the sum when the sum will overflow and for designating for rounding the guard digit of the sum when the sum will not overflow, for designating for rounding the round digit of the difference when the difference will have a leading zero, and for designating for rounding the guard digit of the difference when the difference will not have a leading zero; and means for introducing to the arithmetic unit at the designated digit during the arithmetic combining of the two mantissas an amount equal to one-hal
    Type: Grant
    Filed: March 19, 1984
    Date of Patent: December 31, 1985
    Assignee: Analogic Corporation
    Inventors: Bruno A. Mattedi, Hiromichi Watari
  • Patent number: 4462029
    Abstract: A system for reducing a fixed number of data buses and connections in a computer system having a number of modules connected to the data bus utilizing the internal circuits of the various processing units or modules to transmit data from one unit to another via the data bus when the normal function of a unit can be interrupted, with the data routing and module control being under the control of a command bus.
    Type: Grant
    Filed: December 6, 1979
    Date of Patent: July 24, 1984
    Assignee: Analogic Corporation
    Inventors: Leopold Neumann, Gerald N. Shapiro, Bruno A. Mattedi