Patents by Inventor Bryan Black

Bryan Black has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120098119
    Abstract: A method of manufacturing is provided that includes providing a semiconductor chip device that has a circuit board and a first semiconductor chip coupled thereto. A lid is placed on the circuit board. The lid includes an opening and an internal cavity. A liquid thermal interface material is placed in the internal cavity for thermal contact with the first semiconductor chip and the circuit board.
    Type: Application
    Filed: October 22, 2010
    Publication date: April 26, 2012
    Inventors: Gamal Refai-Ahmed, Michael Z. Su, Bryan Black
  • Publication number: 20120075807
    Abstract: A method of manufacturing is provided that includes placing a thermal management device in thermal contact with a first semiconductor chip of a semiconductor chip device. The semiconductor chip device includes a first substrate coupled to the first semiconductor chip. The first substrate has a first aperture. At least one of the first semiconductor chip and the thermal management device is at least partially positioned in the first aperture.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventors: Gamal Refai-Ahmed, Bryan Black, Michael Z. Su
  • Publication number: 20120074579
    Abstract: A method of manufacturing includes connecting a first end of a first through-silicon-via to a first die seal proximate a first side of a first semiconductor chip. A second end of the first thu-silicon-via is connected to a second die seal proximate a second side of the first semiconductor chip opposite the first side.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventors: Michael Z. Su, Gamal Refai-Ahmed, Bryan Black
  • Publication number: 20120061853
    Abstract: A method of manufacturing is provided that includes placing a removable cover on a surface of a substrate. The substrate includes a first semiconductor chip positioned on the surface. The first semiconductor chip includes a first sidewall. The removable cover includes a second sidewall positioned opposite the first sidewall. A first underfill is placed between the first semiconductor chip and the surface wherein the second sidewall provides a barrier to flow of the first underfill. Various apparatus are also disclosed.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 15, 2012
    Inventors: Michael Z. Su, Lei Fu, Gamal Refai-Ahmed Refai-Ahmed, Bryan Black
  • Publication number: 20120061821
    Abstract: A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 15, 2012
    Inventors: Bryan Black, Michael Z. Su, Gamal Refai-Ahmed, Joe Siegel, Seth Prejean
  • Publication number: 20120061852
    Abstract: A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 15, 2012
    Inventors: Michael Z. Su, Gamal Refai-Ahmed, Bryan Black
  • Publication number: 20120043539
    Abstract: A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is singulated from the semiconductor wafer with at least a portion of the thermal interface tape still attached to the semiconductor chip.
    Type: Application
    Filed: August 20, 2010
    Publication date: February 23, 2012
    Inventors: Seth Prejean, Dales Kent, Ronnie Brandon, Gamal Refai-Ahmed, Michael Z. Su, Michael Bienek, Joseph Siegel, Bryan Black
  • Publication number: 20120043669
    Abstract: A method of assembling a semiconductor chip device is provided that includes providing a circuit board including a surface with an aperture. A portion of a first heat spreader is positioned in the aperture. A stack is positioned on the first heat spreader. The stack includes a first semiconductor chip positioned on the first heat spreader and a substrate that has a first side coupled to the first semiconductor chip.
    Type: Application
    Filed: August 20, 2010
    Publication date: February 23, 2012
    Inventors: Gamal Refai-Ahmed, Michael Z. Su, Bryan Black
  • Publication number: 20120043668
    Abstract: A method of assembling a semiconductor chip device is provided that includes placing an interposer on a first semiconductor chip. The interposer includes a first surface seated on the first semiconductor chip and a second surface adapted to thermally contact a heat spreader. The second surface includes a first aperture. A second semiconductor chip is placed in the first aperture.
    Type: Application
    Filed: August 20, 2010
    Publication date: February 23, 2012
    Inventors: Gamal Refai-Ahmed, Michael Z. Su, Bryan Black, Maxat Touzelbaev, Yizhang Yang
  • Publication number: 20120038061
    Abstract: A semiconductor chip device includes a first semiconductor chip adapted to be stacked with a second semiconductor chip wherein the second semiconductor chip includes a side and first and second conductor structures projecting from the side. The first semiconductor chip includes a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and that has a first lateral dimension and is adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and that has a second lateral dimension larger than the first lateral dimension and is adapted to couple to the other of the first and second conductor structures.
    Type: Application
    Filed: August 14, 2010
    Publication date: February 16, 2012
    Inventors: Michael Z. Su, Gamal Rafai-Ahmed, Bryan Black
  • Publication number: 20110304051
    Abstract: Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support structure on the first semiconductor chip. The heat spreader is positioned proximate the thermal interface material layer. The thermal interface material layer is reflowed to establish thermal contact with both the first semiconductor chip and the heat spreader.
    Type: Application
    Filed: August 23, 2011
    Publication date: December 15, 2011
    Inventors: Maxat Touzelbaev, Gamal Refai-Ahmed, Yizhang Yang, Bryan Black
  • Patent number: 8059441
    Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: November 15, 2011
    Assignee: Intel Corporation
    Inventors: Mohammed H. Taufique, Derwin Jallice, Donald W. McCauley, John P. DeVale, Edward A. Brekelbaum, Jeffrey P. Rupley, II, Gabriel H. Loh, Bryan Black
  • Patent number: 8034662
    Abstract: Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support structure on the first semiconductor chip. The heat spreader is positioned proximate the thermal interface material layer. The thermal interface material layer is reflowed to establish thermal contact with both the first semiconductor chip and the heat spreader.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: October 11, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Maxat Touzelbaev, Gamal Refai-Ahmed, Yizhang Yang, Bryan Black
  • Patent number: 8032711
    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch logic may transfer two or more cache lines from an open page in the DRAM to the SRAM based, at least in part, on the prefetch hint.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: October 4, 2011
    Assignee: Intel Corporation
    Inventors: Bryan Black, Murali M. Annavaram, Donald W. McCauley, John P. Devale
  • Publication number: 20110057677
    Abstract: A method to test and package dies so as to increase overall yield is provided. The method includes performing a wafer test on a first die and mounting the first die on a package substrate to form a partial package, if the wafer test of the first die is successful. The method further includes performing a system test on the partial package including the first die and stacking a second die on the first die if the system test on the partial package and the first die is successful.
    Type: Application
    Filed: September 2, 2010
    Publication date: March 10, 2011
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Bryan BLACK, Joseph Seigel
  • Publication number: 20100237496
    Abstract: Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support structure on the first semiconductor chip. The heat spreader is positioned proximate the thermal interface material layer. The thermal interface material layer is reflowed to establish thermal contact with both the first semiconductor chip and the heat spreader.
    Type: Application
    Filed: March 18, 2009
    Publication date: September 23, 2010
    Inventors: Maxat Touzelbaev, Gamal Refai-Ahmed, Yizhang Yang, Bryan Black
  • Publication number: 20100149849
    Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
    Type: Application
    Filed: February 22, 2010
    Publication date: June 17, 2010
    Inventors: Mohammed Taufique, Derwin Jallice, Donald W. McCauley, John P. DeVale, Edward A. Brekelbaum, Jeffrey P. Rupley, II, Gabriel H. Loh, Bryan Black
  • Patent number: 7692946
    Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: April 6, 2010
    Assignee: Intel Corporation
    Inventors: Mohammed H. Taufique, Derwin Jallice, Donald W. McCauley, John P. DeVale, Edward A. Brekelbaum, Jeffrey P. Rupley, II, Gabriel H. Loh, Bryan Black
  • Patent number: 7620781
    Abstract: Implementation of a Bloom filter using multiple single-ported memory slices. A control value is combined with a hashed address value such that the resultant address value has the property that one, and only one, of the k memories or slices is selected for a given input value, a, for each bank. Collisions are thereby avoided and the multiple hash accesses for a given input value, a, may be performed concurrently. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: November 17, 2009
    Assignee: Intel Corporation
    Inventors: Mauricio Breternitz, Jr., Youfeng Wu, Peter G. Sassone, Jeffrey P. Rupley, II, Wesley Attrot, Bryan Black
  • Publication number: 20090001601
    Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Mohammed H. Taufique, Derwin Jallice, Donald W. McCauley, John P. DeVale, Jeffrey P. Rupley, II, Edward A. Brekelbaum, Gabriel H. Loh, Bryan Black