Patents by Inventor Bryan W. Chin
Bryan W. Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10394730Abstract: Methods and systems are disclosed for routing and distributing interrupts in a multi-processor computer to various processing elements within the computer. A system for distributing the interrupts may include a plurality of logic devices configured in a hierarchical tree structure that distributes incoming interrupts to interrupt redistributors (redistribution devices). The system also includes plural processing elements, where each processing element has an associated bus address. A shared serial bus couples the redistribution devices and processing elements. Each of the redistribution devices is configured to transfer the incoming interrupts to at least one of the processing elements over the common bus, based on the bus address.Type: GrantFiled: November 14, 2014Date of Patent: August 27, 2019Assignee: Cavium, LLCInventors: Bryan W. Chin, Wu Ye, Yoganand Chillarige, Paul G. Scrobohaci, Scott Lurndal
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Patent number: 10042778Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.Type: GrantFiled: March 31, 2017Date of Patent: August 7, 2018Assignee: Cavium, Inc.Inventors: Shubhendu S. Mukherjee, Bryan W. Chin, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler, Christopher Mikulis
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Patent number: 9928193Abstract: A silicon device configured to distribute a global timer value over a single serial bus to a plurality of processing elements that are disposed on the silicon device and that are coupled to the serial bus. Each of the processing elements comprises a slave timer. Upon receipt of the global timer value, the processing elements synchronize their respective slave timers with the global timer value. After the timers are synchronized, the global timer sends periodic increment signals to each of the processing elements. Upon receipt of the increment signals, the processing elements update their respective slave timers.Type: GrantFiled: November 14, 2014Date of Patent: March 27, 2018Assignee: Cavium, Inc.Inventors: Frank Worrell, Bryan W. Chin
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Publication number: 20170206171Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.Type: ApplicationFiled: March 31, 2017Publication date: July 20, 2017Inventors: Shubhendu S. Mukherjee, Bryan W. Chin, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler, Christopher Mikulis
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Patent number: 9703669Abstract: One disclosed embodiment provides an integrated circuit that has a plurality of processors and a plurality of processor trace collection logic units. Each processor trace collection logic unit corresponds with, and is operatively coupled to, one of the processors. A separate filtering logic unit is operatively coupled to the plurality of processor trace collection logic units. In some embodiments of the integrated circuit, each processor trace collection logic unit is operative to continuously collect processor trace information from a corresponding operatively coupled processor. Each filtering logic unit is operative to monitor the continuous processor trace information for occurrence of a predetermined condition, and to store some of the processor trace information to memory in response to occurrence of that condition.Type: GrantFiled: November 14, 2014Date of Patent: July 11, 2017Assignee: CAVIUM, Inc.Inventors: Gerald Lampert, David Kravitz, Bryan W. Chin
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Patent number: 9645941Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.Type: GrantFiled: September 26, 2013Date of Patent: May 9, 2017Assignee: CAVIUM, INC.Inventors: Shubhendu S. Mukherjee, Bryan W. Chin, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler, Christopher Mikulis
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Patent number: 9639476Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache.Type: GrantFiled: September 26, 2013Date of Patent: May 2, 2017Assignee: CAVIUM, INC.Inventors: Bryan W. Chin, Shubhendu S. Mukherjee, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler
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Patent number: 9568944Abstract: Multiple ARM devices, each having multiple processing elements, linked together by an interconnect to form a coherent memory fabric in which each device has access to all of the processing elements located on all of the devices that are part of the coherent memory fabric. In order to comply with the ARM architecture, the system must have a global timer that is accessible to all of the ARM devices so that each of the devices can maintain the same timer value. The devices, systems, and methods disclosed herein provide for initial synchronization between multiple ARM devices that are joined together to form a coherent memory fabric. The initial synchronization is achieved by determining an offset between the timers of each ARM device and then minimizing the offset. The synchronization may be periodically checked and adjusted, as necessary, to maintain proper synchronization.Type: GrantFiled: November 14, 2014Date of Patent: February 14, 2017Assignee: CAVIUM, INC.Inventors: Frank Worrell, Bryan W. Chin
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Patent number: 9404970Abstract: A system includes processor cores that receive packets over a debug bus. The cores execute transactions in response to the packets. The packets are one of several types of packets such as a Second Access Bus (SAB) packet and Debug Access Bus (DAB) packet. The cores include specified resources and non-specified resources. A core that executes a transaction in response to a SAB packet accesses a non-specified resource and a core that executes a transaction in response to a DAB packet accesses a specified resources. A debug specification identifies the specified resources as being accessible by a debug controller. The debug specification does not identify the non-specified resources as being accessible by the debug controller.Type: GrantFiled: November 14, 2014Date of Patent: August 2, 2016Assignee: CAVIUM, INC.Inventors: Teng Chiang Lin, Gerald Lampert, Nitin Prakash, Andy Wang, Bryan W. Chin
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Patent number: 9372800Abstract: A multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of providing memory coherence within the multi-chip system comprises maintaining, at a first chip device of the multi-chip system, state information indicative of one or more states of one or more copies, residing in one or more chip devices of the multi-chip system, of a data block. The data block is stored in a memory associated with one of the multiple chip devices. The first chip device receives a message associated with a copy of the one or more copies of the data block from a second chip device of the multiple chip devices, and, in response, executes a scheme of one or more actions determined based on the state information maintained at the first chip device and the message received.Type: GrantFiled: March 7, 2014Date of Patent: June 21, 2016Assignee: Cavium, Inc.Inventors: Isam Akkawi, Richard E. Kessler, David H. Asher, Bryan W. Chin, Wilson P. Snyder, II
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Publication number: 20160140064Abstract: Methods and systems are disclosed for routing and distributing interrupts in a multi-processor computer to various processing elements within the computer. A system for distributing the interrupts may include a plurality of logic devices configured in a hierarchical tree structure that distributes incoming interrupts to interrupt redistributors (redistribution devices). The system also includes plural processing elements, where each processing element has an associated bus address. A shared serial bus couples the redistribution devices and processing elements. Each of the redistribution devices is configured to transfer the incoming interrupts to at least one of the processing elements over the common bus, based on the bus address.Type: ApplicationFiled: November 14, 2014Publication date: May 19, 2016Inventors: Bryan W. CHIN, Wu YE, Yoganand CHILLARIGE, Paul G. SCROBOHACI, Scott LURNDAL
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Publication number: 20160139201Abstract: A system includes processor cores that receive packets over a debug bus. The cores execute transactions in response to the packets. The packets are one of several types of packets such as a Second Access Bus (SAB) packet and Debug Access Bus (DAB) packet. The cores include specified resources and non-specified resources. A core that executes a transaction in response to a SAB packet accesses a non-specified resource and a core that executes a transaction in response to a DAB packet accesses a specified resources. A debug specification identifies the specified resources as being accessible by a debug controller. The debug specification does not identify the non-specified resources as being accessible by the debug controller.Type: ApplicationFiled: November 14, 2014Publication date: May 19, 2016Inventors: Teng Chiang Lin, Gerald Lampert, Nitin Prakash, Andy Wang, Bryan W. Chin
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Publication number: 20160140014Abstract: One disclosed embodiment provides an integrated circuit that has a plurality of processors and a plurality of processor trace collection logic units. Each processor trace collection logic unit corresponds with, and is operatively coupled to, one of the processors. A separate filtering logic unit is operatively coupled to the plurality of processor trace collection logic units. In some embodiments of the integrated circuit, each processor trace collection logic unit is operative to continuously collect processor trace information from a corresponding operatively coupled processor. Each filtering logic unit is operative to monitor the continuous processor trace information for occurrence of a predetermined condition, and to store some of the processor trace information to memory in response to occurrence of that condition.Type: ApplicationFiled: November 14, 2014Publication date: May 19, 2016Inventors: Gerald Lampert, David Kravitz, Bryan W. Chin
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Publication number: 20160139625Abstract: Multiple ARM devices, each having multiple processing elements, linked together by an interconnect to form a coherent memory fabric in which each device has access to all of the processing elements located on all of the devices that are part of the coherent memory fabric. In order to comply with the ARM architecture, the system must have a global timer that is accessible to all of the ARM devices so that each of the devices can maintain the same timer value. The devices, systems, and methods disclosed herein provide for initial synchronization between multiple ARM devices that are joined together to form a coherent memory fabric. The initial synchronization is achieved by determining an offset between the timers of each ARM device and then minimizing the offset. The synchronization may be periodically checked and adjusted, as necessary, to maintain proper synchronization.Type: ApplicationFiled: November 14, 2014Publication date: May 19, 2016Inventors: Frank Worrell, Bryan W. Chin
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Publication number: 20160140066Abstract: A silicon device configured to distribute a global timer value over a single serial bus to a plurality of processing elements that are disposed on the silicon device and that are coupled to the serial bus. Each of the processing elements comprises a slave timer. Upon receipt of the global timer value, the processing elements synchronize their respective slave timers with the global timer value. After the timers are synchronized, the global timer sends periodic increment signals to each of the processing elements. Upon receipt of the increment signals, the processing elements update their respective slave timers.Type: ApplicationFiled: November 14, 2014Publication date: May 19, 2016Inventors: Frank Worrell, Bryan W. Chin
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Patent number: 9268694Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB is an additional cache storing collapsed translations derived from the MTLB. Entries in the MTLB, the collapsed TLB, and other caches can be maintained for consistency.Type: GrantFiled: September 26, 2013Date of Patent: February 23, 2016Assignee: Cavium, Inc.Inventors: Wilson P. Snyder, II, Bryan W. Chin, Shubhendu S. Mukherjee, Michael Bertone, Richard E. Kessler
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Patent number: 9208103Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Lookups to the caches of the MTLB can be selectively bypassed based on a control configuration and the attributes of a received address.Type: GrantFiled: September 26, 2013Date of Patent: December 8, 2015Assignee: Cavium, Inc.Inventors: Richard E. Kessler, Bryan W. Chin, Michael Bertone
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Publication number: 20150254183Abstract: A multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of providing memory coherence within the multi-chip system comprises maintaining, at a first chip device of the multi-chip system, state information indicative of one or more states of one or more copies, residing in one or more chip devices of the multi-chip system, of a data block. The data block is stored in a memory associated with one of the multiple chip devices. The first chip device receives a message associated with a copy of the one or more copies of the data block from a second chip device of the multiple chip devices, and, in response, executes a scheme of one or more actions determined based on the state information maintained at the first chip device and the message received.Type: ApplicationFiled: March 7, 2014Publication date: September 10, 2015Applicant: Cavium, Inc.Inventors: Isam Akkawi, Richard E. Kessler, David H. Asher, Bryan W. Chin, Wilson P. Snyder, II
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Publication number: 20150089150Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Lookups to the caches of the MTLB can be selectively bypassed based on a control configuration and the attributes of a received address.Type: ApplicationFiled: September 26, 2013Publication date: March 26, 2015Applicant: Cavium, Inc.Inventors: Richard E. Kessler, Bryan W. Chin, Michael Bertone
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Publication number: 20150089116Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache.Type: ApplicationFiled: September 26, 2013Publication date: March 26, 2015Applicant: Cavium, Inc.Inventors: Bryan W. Chin, Shubhendu S. Mukherjee, Wilson P. Snyder, II, Michael Bertone, Richard E. Kessler