Patents by Inventor Budong You

Budong You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10332804
    Abstract: The present disclosure relates to a method for manufacturing a CM OS structure. Shallow trench isolation is formed in a semiconductor substrate. A first region is defined for a first MOSFET and a second MOSFET of a first type and a second region is defined for a third MOSFET and a fourth MOSFET of a second type, by shallow trench isolation. First to fourth Gates sacks are formed on the semiconductor substrate, each of which includes a gate conductor and a gate dielectric and the gate dielectric is disposed between the gate conductor and the semiconductor substrate. The first and second gate stacks are formed in the first region, and the third and fourth gate stacks are formed in the second region. The gate dielectrics of the first and third gate stacks have a first thickness, and the gate dielectrics of the second and fourth gate stacks have a second thickness larger than the first thickness. Some masks are commonly used in various steps in this process so that the number of the masks is reduced.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: June 25, 2019
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
    Inventors: Budong You, Zheng Lyu, Xianguo Huang, Chuan Peng
  • Publication number: 20180277447
    Abstract: The present disclosure relates to a method for manufacturing a CMOS structure. A first gate stack is formed on a semiconductor substrate in a first region. A second gate stack is formed on the semiconductor substrate in a second region. A dopant of a first type is implanted with the first gate stack and the second gate stack as a hard mask to form a lightly-doped drain region of the first type. A dopant of a second type is implanted by using a first mask and with the second gate stack as a hard mask to form a lightly-doped drain region of the second type. The first mask blocks the first region and exposes the second region. When the lightly-doped drain region of the second type is formed, the dopant of the second type over dopes a predetermined region of the lightly-doped drain region of the first type. In such a process, over doping is used for reducing the number of masks. A doping concentration of a well region may be modified to adjust work function.
    Type: Application
    Filed: June 1, 2018
    Publication date: September 27, 2018
    Inventors: Budong You, Zheng Lyu, Xianguo Huang, Chuan Peng
  • Publication number: 20170256532
    Abstract: Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.
    Type: Application
    Filed: May 17, 2017
    Publication date: September 7, 2017
    Inventors: David Lidsky, Ognjen Djekic, Ion Elinor Opris, Budong You, Anthony J. Stratakos, Alexander Ikriannikov, Biljana Beronja, Trey Roessig
  • Patent number: 9679885
    Abstract: Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: June 13, 2017
    Assignee: Volterra Semiconductor Corporation
    Inventors: David Lidsky, Ognjen Djekic, Ion Opris, Budong You, Anthony J. Stratakos, Alexander Ikriannikov, Biljana Beronja, Trey Roessig
  • Patent number: 9627513
    Abstract: The present disclosure relates to a lateral double-diffused metal oxide semiconductor transistor and a method for manufacturing the same. In the method, a high-voltage gate dielectric is formed at a surface of a semiconductor layer. A thin gate dielectric is formed above the substrate and has at least a portion adjacent to the high-voltage gate dielectric. A gate conductor is formed above the thin gate dielectric and the high-voltage gate dielectric. A first mask is used for patterning the gate conductor to define a first sidewall of the gate conductor above the thin gate dielectric. A second mask is used for patterning the gate conductor to define a second sidewall of the gate conductor at least partially above the high-voltage gate dielectric. Source and drain regions are formed to have a first doping type. The method further comprises doping through the first mask to form a body region of a second doping type. The second doping type is opposite to the first doping type.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: April 18, 2017
    Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
    Inventors: Budong You, Meng Wang, Zheng Lyu
  • Publication number: 20160087081
    Abstract: The present disclosure relates to a lateral double-diffused metal oxide semiconductor transistor and a method for manufacturing the same. In the method, a high-voltage gate dielectric is formed at a surface of a semiconductor layer. A thin gate dielectric is formed above the substrate and has at least a portion adjacent to the high-voltage gate dielectric. A gate conductor is formed above the thin gate dielectric and the high-voltage gate dielectric. A first mask is used for patterning the gate conductor to define a first sidewall of the gate conductor above the thin gate dielectric. A second mask is used for patterning the gate conductor to define a second sidewall of the gate conductor at least partially above the high-voltage gate dielectric. Source and drain regions are formed to have a first doping type. The method further comprises doping through the first mask to form a body region of a second doping type. The second doping type is opposite to the first doping type.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 24, 2016
    Inventors: Budong You, Meng Wang, Zheng Lyu
  • Publication number: 20160043004
    Abstract: The present disclosure relates to a method for manufacturing a CMOS structure. A first gate stack is formed on a semiconductor substrate in a first region. A second gate stack is formed on the semiconductor substrate in a second region. A dopant of a first type is implanted with the first gate stack and the second gate stack as a hard mask to form a lightly-doped drain region of the first type. A dopant of a second type is implanted by using a first mask and with the second gate stack as a hard mask to form a lightly-doped drain region of the second type. The first mask blocks the first region and exposes the second region. When the lightly-doped drain region of the second type is formed, the dopant of the second type over dopes a predetermined region of the lightly-doped drain region of the first type. In such a process, over doping is used for reducing the number of masks. A doping concentration of a well region may be modified to adjust work function.
    Type: Application
    Filed: August 11, 2015
    Publication date: February 11, 2016
    Inventors: Budong You, Zheng Lyu, Xianguo Huang, Chuan Peng
  • Publication number: 20160043005
    Abstract: The present disclosure relates to a method for manufacturing a CM OS structure. Shallow trench isolation is formed in a semiconductor substrate. A first region is defined for a first MOSFET and a second MOSFET of a first type and a second region is defined for a third MOSFET and a fourth MOSFET of a second type, by shallow trench isolation. First to fourth Gates sacks are formed on the semiconductor substrate, each of which includes a gate conductor and a gate dielectric and the gate dielectric is disposed between the gate conductor and the semiconductor substrate. The first and second gate stacks are formed in the first region, and the third and fourth gate stacks are formed in the second region. The gate dielectrics of the first and third gate stacks have a first thickness, and the gate dielectrics of the second and fourth gate stacks have a second thickness larger than the first thickness. Some masks are commonly used in various steps in this process so that the number of the masks is reduced.
    Type: Application
    Filed: August 11, 2015
    Publication date: February 11, 2016
    Inventors: Budong You, Zheng Lyu, Xianguo Huang, Chuan Peng
  • Patent number: 9224603
    Abstract: A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain. The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: December 29, 2015
    Assignee: Volterra Semiconductor LLC
    Inventors: Yang Lu, Budong You, Marco A. Zuniga, Hamza Yilmaz
  • Patent number: 9078381
    Abstract: Methods and apparatuses related to packaging a monolithic voltage regulator are disclosed. In one embodiment, an apparatus includes: (i) a monolithic voltage regulator with a transistor arranged as parallel transistor devices; (ii) bumps on the monolithic voltage regulator to form connections to source and drain terminals of the transistor; (iii) a single layer lead frame with a plurality of interleaving lead fingers coupled to the monolithic voltage regulator via the bumps, where the single layer lead frame includes first and second surfaces, where the first surface includes a first pattern to form connections to the bumps, and where the second surface includes a second pattern that is different from the first pattern; and (iv) a flip-chip package encapsulating the monolithic voltage regulator, the bumps, and the single layer lead frame, where the flip-chip package has external connectors of the monolithic voltage regulator at the second surface of the single layer lead frame.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: July 7, 2015
    Assignees: Silergy Technology, Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Budong You
  • Patent number: 8994106
    Abstract: A transistor structure includes a p-type substrate, an n-well implanted in the substrate, a p-doped p-body implanted in the n-well, first and second transistors, an input line, and an output line. The first transistor includes a first gate, a first source, and a first drain, and the second transistor includes a second gate, a second source, and a second drain. The first source includes a first p+ region and a first n+ region, and the first drain includes a second n+ region. The second source includes a third n+ region and a second p+ region, and the second drain includes a third p+ region. The input line connects the first gate and the second gate, and the output line connects the second n+ region and the third p+ region.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: March 31, 2015
    Assignee: Volterra Semiconductor LLC
    Inventors: Budong You, Marco A. Zuniga
  • Patent number: 8936980
    Abstract: Method and apparatus for providing a lateral double-diffused MOSFET (LDMOS) transistor having a dual gate. The dual gate includes a first gate and a second gate. The first gate includes a first oxide layer formed over a substrate, and the second gate includes a second oxide layer formed over the substrate. The first gate is located a pre-determined distance from the second gate. A digitally implemented voltage regulator is also provided that includes a switching circuit having a dual gate LDMOS transistor.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: January 20, 2015
    Assignee: Volterra Semiconductor LLC
    Inventors: Marco A. Zuniga, Budong You
  • Patent number: 8912600
    Abstract: Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can include: (i) an n-doped deep n-well (DNW) region on a substrate; (ii) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region; (iii) a conductive gate over the gate oxide and a portion of the drain oxide; (iv) a p-doped p-body region in the source region; (v) an n-doped drain region in the drain region; (vi) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and (vii) a second n-doped n+ region in the drain region.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: December 16, 2014
    Assignees: Silergy Technology, Silergy Semiconductor Technology (Hang-Zhou) Ltd
    Inventor: Budong You
  • Publication number: 20140151800
    Abstract: A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain.
    Type: Application
    Filed: February 7, 2014
    Publication date: June 5, 2014
    Applicant: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga
  • Publication number: 20140134834
    Abstract: A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain. The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.
    Type: Application
    Filed: January 21, 2014
    Publication date: May 15, 2014
    Applicant: Volterra Semiconductor Corporation
    Inventors: Yang Lu, Budong You, Marco A. Zuniga, Hamza Yilmaz
  • Patent number: 8716795
    Abstract: Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, a method of fabricating an LDMOS transistor with source, drain, and gate regions on a substrate, can include: forming p-type and n-type buried layer (PBL, NBL) regions; growing an epitaxial (N-EPI) layer on the NBL/PBL regions; forming a p-doped deep p-well (DPW) region on the PBL region; forming a well region in the N-EPI layer; forming a doped body region; forming an active area and a field oxide (FOX) region, and forming a drain oxide between the source and drain regions of the LDMOS transistor; forming a gate oxide adjacent to the source and drain regions, and forming a gate on the gate oxide and a portion of the drain oxide; and forming a doped drain region, and first and second doped source regions.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: May 6, 2014
    Assignees: Silergy Technology, Silergy Semiconductor Technology (Hangzhou) Ltd.
    Inventor: Budong You
  • Patent number: 8698242
    Abstract: A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: April 15, 2014
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga
  • Patent number: 8664728
    Abstract: A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: March 4, 2014
    Assignee: Volterra Semiconductor Corporation
    Inventors: Yang Lu, Budong You, Marco A. Zuniga, Hamza Yilmaz
  • Patent number: 8574973
    Abstract: An integrated circuit structure having an LDMOS transistor and a CMOS transistor includes a p-type substrate having a surface, an n-well implanted in the substrate, the first n-well providing a CMOS n-well, a CMOS transistor including a CMOS source with a first p+ region implanted in the n-well, a CMOS drain with a second p+ region implanted in the n-well, and a CMOS gate between the first p+ region and the second p+ region, and an LDMOS transistor including an LDMOS source with an LDMOS source including a p-body implanted in the n-well, a third p+ region implanted in the p-body, and a first n+ region implanted in the p-body, an LDMOS drain including an n-doped shallow drain implanted in the n-well, and a second n+ region implanted in the n-doped shallow drain, and an LDMOS gate between the third p+ region and the second n+ region.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 5, 2013
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga
  • Publication number: 20130234249
    Abstract: An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.
    Type: Application
    Filed: April 24, 2013
    Publication date: September 12, 2013
    Applicant: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Budong You, Yang Lu