Abstract: A transmission apparatus capable of transferring data between a transmitting and a receiving device using a small-scale, low-cost hardware implementation for high-speed data transmission, the apparatus being conducive to reducing the amount of system design work on a target system. The transmitting device sends to the receiving device both data and a reference signal generated by a reference signal generation circuit. On the receiving side, a phase adjustment circuit delays the reference signal and a phase determination/phase amount control circuit brings the delayed signal into phase with a receiving-side clock signal. A data signal group is given the same amount of delay as the reference signal. The scheme allows data signals to be received directly in keeping with the receiving-side clock signal, eliminating the need for strict clock skew management, massive detours of data transmission lines or a wasteful wait time required for signal values to be established.

Abstract: In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.

Abstract: In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.

Abstract: A variable delay circuit including delay devices each having a plurality of delay units connected successively, only some of the delay units of the delay devices being connected to a signal transmission line, wherein a delay time is controlled by activating or inactivating the plurality of delay units according to control signals applied to control input terminals provided respectively for said plurality of delay units.

Abstract: The invention relates to method and apparatus for adjusting a clock signal which is supplied to an electronic apparatus. After the turn-on of a power source of the electronic apparatus, it is detected that a temperature of at least a part of devices in the electronic apparatus substantially reaches a saturation state. When the temperature of the device reaches the saturation state, a phase adjustment of the clock signal of the electronic apparatus is executed. After completion of the phase adjustment of the clock signal, its adjusting state is fixed.

Abstract: The present invention provides a clock signal supply method and system. A reference signal and a synchronizing signal are generated, as well as a clock signal, at a clock signal generating source end. Both the reference signal and the synchronizing signal have a period longer than that of the clock signal. The clock signal at a clock signal destination end is frequency divided in synchronism with the synchronizing signal to provide a sample to be compared with the reference signal. The resultant frequency-divided signal is compared with the reference signal in phase. A delay control is made for the clock signal in accordance with the result of the comparison to adjust the phase of the clock signal at the signal destinations.

Abstract: A power supply device has its power supply conductor bars, in which a.c. currents caused by a.c. noises flow in the same direction, laid closely in parallel while retaining their insulation thereby to increase the total inductance so that the impedance increases without accompanied by an increase in the d.c. resistance of the power supply conductor bars. An increased coupling impedance of the power supply conductor bars effectively attenuates the a.c. noises from d.c. power units, which then supply d.c. power with reduced a.c. noises to an electronic apparatus such as a computer through the power supply device.

Abstract: The present invention relates to a clock signal supplying device provided with an automatic phase regulating function for preventing errors in the phase regulation due to noise. In the device according to the present invention, there is disposed a reference signal serving as a phase reference, and transmission lines for clock signals and a transmission line for the reference signal are disposed from a clock signal supplying source to devices which are destinations of the distribution of clock signals. The transmission line for the reference signal is adjusted in advance so as to produce no skew. In the device, which is the destination of distribution of the clock signal, there is disposed a variable delay circuit for regulation of the phase of the clock signal and a phase comparing circuit for comparing the output of the variable delay circuit with the phase of the reference signal to output the result of the comparison.

Abstract: A system for feeding clock signals to a plurality of load units comprises an oscillator for generating a first clock signal having a predetermined frequency, a plurality of signal lines for transmitting a signal representative of the first clock signal to a plurality of load units, and delays assigned to the plurality of signal lines for adjusting phases of the signal transmitted on a corresponding line at connection points between the oscillator and the load unit. Each load unit is responsive to the signal transmitted on a corresponding signal line for producing second clock signals with a frequency n times greater than that of the second clock signals where n is an integer greater than one. Each load unit further is responsive to the second clock signal for generating a plurality of third clock signals which have discrete phases. The plurality of load units are synchronized with at least one of the plurality of third clock signals.

Abstract: An ordinary differential type gate circuit has two transistors to which complementary inputs are given and which are turned on and off, and complementary type outputs in accordance with the states of the complementary inputs are generated from the collectors of those transistors. In this invention, there are further added a fixed threshold type gate circuit to which is inputted a control signal and a circuit which, when the control signal is inputted to this fixed threshold type gate circuit, generates complementary outputs in constant states irrespective of the states of the complementary inputs in response to the state of the control signal, thereby preventing the inputs applied to the differential type gate circuit from being reflected to the outputs.