Abstract: A method of making semiconductor package and the package comprising the steps of providing a base having a plurality of cavities therein, forming a plurality of sets of spaced apart first apertures extending entirely through the base, each of the sets of spaced apart first apertures surrounding one of the cavities, forming a plurality of sets of second apertures extending partially through the base, each of the second apertures of a set being interconnected with a pair of adjacent ones of the first apertures from one of the sets to form a continuous groove extending partially through the base and surrounding one of the cavities and then causing the second apertures to extend entirely through the base to form individual packages associated with each of the cavities. The base is a cast base and the first and second apertures are preferably said base.

Abstract: A heat exchanger and method for cooling power electronics modules. The power electronics module transferring heat generated during operation to the heat exchanger through a thermal base of the power module. The heat exchanger being directly bonded to the thermal base and comprising a metal foam. The metal foam having a network of metal ligaments forming numerous open cells to provide porosity. The metal ligaments are aligned to provide a higher metal density in cross-sectional planes of the foam perpendicular to the intended direction of heat flow.

Abstract: A method of power electronic packaging includes a practicable and reliable method of fabricating power circuit modules and associated connections that are compatible with the standard top layer metalization of commercially available power devices. A planar single- or multi-layer membrane structure is attached to a carrier frame, and a via pattern is formed in the membrane. Power devices are aligned and attached to the planar membrane structure; a top layer interconnect structure is formed by metalizing the vias and the film; and a circuit is formed by patterning a deposited metal layer. The carrier frame is removed, and upper and lower thermal base plate sub-assemblies are attached to the power device-on-membrane structure. The planar device-on-membrane structure accommodates different types of power devices having variations in thickness. The thermal base plate sub-assemblies may include integral, high-performance heat exchangers for providing a low thermal resistance path to the ambient.

Abstract: A method of metalizing a ceramic member (e.g., lid or thermal base) for a semiconductor power device with a film of aluminum in an ion vapor deposition chamber in which an argon ion cloud is formed around the member within the chamber by biasing the member with a voltage and in which a continuous source of aluminum vapor is provided within the chamber so that aluminum ions are available to be accelerated towards the member from plural directions by the bias voltage, the aluminum ions being formed from the aluminum vapor upon passage through the argon ion cloud. The member may be an array of plates that are metalized before being separated. The metalized plates may be used as lids for semiconductor device packages or as thermal bases for power modules.

Abstract: A method of power electronic packaging includes a practicable and reliable method of fabricating power circuit modules and associated connections that are compatible with the standard top layer metalization of commercially available power devices. A planar single- or multi-layer membrane structure is attached to a carrier frame, and a via pattern is formed in the membrane. Power devices are aligned and attached to the planar membrane structure; a top layer interconnect structure is formed by metalizing the vias and the film; and a circuit is formed by patterning a deposited metal layer. The carrier frame is removed, and upper and lower thermal base plate sub-assemblies are attached to the power device-on-membrane structure. The planar device-on-membrane structure accommodates different types of power devices having variations in thickness. The thermal base plate sub-assemblies may include integral, high-performance heat exchangers for providing a low thermal resistance path to the ambient.

Abstract: A heat exchanger and method for cooling power electronics modules. The power electronics module transferring heat generated during operation to the heat exchanger through a thermal base of the power module. The heat exchanger being directly bonded to the thermal base and comprising a metal foam. The metal foam having a network of metal ligaments forming numerous open cells to provide porosity. The metal ligaments are aligned to provide a higher metal density in cross-sectional planes of the foam perpendicular to the intended direction of heat flow.

Abstract: A method of making a semiconductor package and the package comprising the steps of providing a base having a plurality of cavities therein, forming a plurality of sets of spaced apart first apertures extending entirely through the base, each of the sets of spaced apart first apertures surrounding one of the cavities, forming a plurality of sets of second apertures extending partially through the base, each of the second apertures of a set being interconnected with a pair of adjacent ones of the first apertures from one of the sets to form a continuous groove extending partially through the base and surrounding one of the cavities and then causing the second apertures to extend entirely through the base to form individual packages associated with each of the cavities. The base is a cast base and the first and second apertures are preferably cast into said base.

Abstract: A thermal core (10) including aluminum layer (12) held between two molybdenum layers (14) for dissipating heat from a plurality of chip carriers (22). Core (10) has the ability to withstand excessive vibrational loads while being lightweight. Bonding molybdenum/aluminum/molybdenum layers (12, 14) creates a core (10) having an increased stiffness factor which surpasses military vibrational requirements. Additionally, due to the low density of porous aluminum layer (12), weight limitations set forth by the military can also be met.

Abstract: A system for dissipating heat from semiconductor chips disposed on a substrate which may individually produce differing amounts of heat, the substrate secured to a device uniformly distributing the heat produced by the chips thereover in the form of a metal matrix composite of a thermally conductive material, preferably aluminum or copper, having layers of uniformly spaced fibers, preferably carbon, with a higher thermal conductivity than the metal of the metal matrix and embedded therein. Each layer has a plurality of such fibers in rows, each layer being orthogonal to the layers thereabove and therebelow. Preferably, none of the carbon fibers touch each other. The metal matrix is secured to a heat dissipating structure in the form of a housing having a sponge secured therein. The sponge is preferably of aluminum or copper and has a cellular structure, the cells having interconnecting porosity.

Abstract: A thermal core (10) comprising a graphite layer (12) held between two molybdenum layers (14) for dissipating heat from a plurality of chip carriers 22. Core 10 has the ability to withstand excessive vibrational loads while being light weight. Bonding molybdenum/graphite/molybdenum layers (12, 14) creates a core (10) having an increased stiffness factor which surpasses military vibrational requirements. By using a titanium layer (16) to braze graphite layer (12) and molybdenum layers (14), plating for preventing corrosion attack is not necessary.

Abstract: An electronic system having a first printed wiring board, a first integrated circuit carrier positionable on the printed wiring board and a substrate having a central portion formed of ceramic material. The substrate central portion has a specific thermal conductivity greater than 1.5.times.10.sup.-5 Wm.sup.2 /g.degree.C. The substrate may comprise a ceramic material formed in combination with a modifier of the type which increases fracture toughness thereby inhibiting crack initiation and growth. In an alternate form of the invention the elctronic system includes a substrate having a central portion formed of ceramic material and first and second opposing surfaces each clad with a metallic layer of predetermined thickness.

Abstract: An integrated circuit chip packaging structure, preferably having a semiconductor base substrate, i.e., silicon or gallium arsenide, alternating insulation and conductive layers on the base structure, at least two conductive layers being patterned into thin film wiring (i.e., thin film copper of approximately 5 microns), semiconductor integrated circuit chips connected to the upper-most patterned conductive layer, and means to connected the packaging structure to the next level of packaging (i.e., board or card).The thin film wiring layers typically each having coplanar ground, power and signal lines, with at least one power or ground line existing between coplanar signal lines to minimize cross talk. To facilitate efficient power distribution, lines of specific power levels of the patterned planes are connected to lines of the same power level on other patterned planes to form three dimensional power planes.

Abstract: A self-contained method and structure for partitioning, testing and diagnosing a multi-chip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multi-chip package except for the chip or chips under test, creating a signature of the chip or chips under test by generating and applying random patterns to the chip or chips under test (referred to as the unit under test) and comparing the signature obtained to a "good machine" simulation signature. The structure comprises means for accomplishing the above method steps. A preferred structure comprises an semiconductor substrate having redundant self test circuitry built in and chips having ECIPT circuitry mounted on the semiconductor substrate. Either all or a portion of the self test circuitry, including the required multiplexers, etc., may be incorporated into the semiconductor substrate. ECIPT circuitry may also be built into the substrate below each chip site.

Abstract: A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the conductive layers are wiring means which are adapted for maintaining an extremely low noise level in the package. The low noise level and low resistance and capacitance of the wiring means allows a plurality of discrete semiconductor segments to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent's Rule. Each integrated circuit structure of the present invention emulates a large chip or wafer scale integration structure in performance without having to yield the large chip or wafer, and without redundancy schemes.