Patents by Inventor Burnell G. West

Burnell G. West has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6622107
    Abstract: An apparatus compares propagation delay of electronic by using flip-flops or similar storage elements. The apparatus includes a strobe source having an output line coupled to a control terminal of a pattern source and an input terminal of a variable clock delay. The strobe source triggers the pattern source to output signal a sequence of signals to an input terminal of an element or device under test (DUT). The DUT propagates the signals to a flip-flop. The output signal of the flip-flop is captured after a delay. The propagation delay of the DUT is determined by coinciding the clock signal edge with the data signal edge to the flip-flop so that the flip-flop enters the ambiguity region. Once the delay settings that define the ambiguity region under the same delay are determined for various DUTs, they are compared to determine which DUT has the least propagation delay.
    Type: Grant
    Filed: August 25, 2000
    Date of Patent: September 16, 2003
    Assignee: NPTest LLC
    Inventor: Burnell G. West
  • Publication number: 20030139899
    Abstract: A circuit and related method for distributing events in an event stream (i.e., an electronic signal having a plurality of rising edge transitions and falling edge transitions). The circuit distributes the events in a primary event stream across multiple secondary event streams in such a way that the event rate in each of the secondary event streams is lower than the event rate in the primary event stream, but the relative timing of the events in the primary event stream is maintained in each of the secondary event streams. The secondary event streams can then be provided to respective timestamp circuits, which record the times at which events occur in the secondary event streams. Since the relative timing of the events in the primary event stream is maintained in each of the secondary event streams, the multiple timestamp circuits collectively record the times at which events occur in the primary event stream. The circuit and related method can be used when debugging/testing semiconductor devices.
    Type: Application
    Filed: January 23, 2002
    Publication date: July 24, 2003
    Inventor: Burnell G. West
  • Publication number: 20030105607
    Abstract: Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.
    Type: Application
    Filed: August 16, 2002
    Publication date: June 5, 2003
    Inventors: Michael F. Jones, Robert Whyte, Jamie S. Cullen, Naveed Zaman, Yann Gazounaud, Burnell G. West
  • Publication number: 20030057990
    Abstract: A pin electronics circuit for use in automatic test equipment may include a reconfigurable logic device in which different logic configurations may be installed to make measurements according to multiple tests to be applied to a device under test; a level generating circuit coupled to the reconfigurable logic device, and configured to generate a number of test levels and a number of reference levels; and a switching circuit, coupled to the reconfigurable logic device and the level generating circuit, configured to receive the test levels and the reference levels, and controlled by the reconfigurable logic device to selectively apply the test levels to the device under test according to a selected test and to sense levels inputted to or outputted from the device under test by comparing the reference levels generated by the level generating circuit to the levels inputted to our outputted from the device under test..
    Type: Application
    Filed: August 9, 2002
    Publication date: March 27, 2003
    Inventor: Burnell G. West
  • Publication number: 20030033556
    Abstract: A test system formatter may include a programmable drive circuit configurable to operate in any of a plurality of drive modes, each mode corresponding to a different combination of drive signals or drive timing markers or both, and a programmable response circuit configurable to operate in any of a plurality of strobe modes, each strobe mode corresponding to a different combination of strobe signals. The formatter may also include multiple drive channels and/or multiple response channels, each channel being formed, e.g., of an event logic interface and a corresponding linear delay element. The drive channels provide signals to the drive circuit to be used to generate drive signals or drive timing markers or both. The response channels receive from one or more pin-electronics comparators response signals used to generate fail outputs. The programmable drive and response circuits are configurable to route signals through multiple channels in parallel.
    Type: Application
    Filed: March 18, 2002
    Publication date: February 13, 2003
    Inventor: Burnell G. West
  • Publication number: 20030005360
    Abstract: Generating test signals for a device under test (DUT) involves generating a master reference signal, using a vernier technique to generate test pattern signals based on the master reference signal, generating a test clock signal that is phase-matched with and frequency similar to the test pattern signals by providing the master reference signal as input to a phase-locked loop (PLL) and controlling one or more programmable dividers in the PLL to adjust the test clock signal to be a multiple or sub-multiple of a frequency of the test pattern signals, applying the test clock signal to the clock input pin of the DUT, and applying the test pattern signals to data pins of the DUT. When the frequency of the test pattern signals is changed, the test clock signal frequency may be adjusted to calibrate to the changed frequency of the test pattern signals by re-programming the programmable dividers.
    Type: Application
    Filed: March 19, 2002
    Publication date: January 2, 2003
    Inventors: Burnell G. West, Paolo Dalla Ricca
  • Patent number: 6501706
    Abstract: A time-to-digital converter records the arrival times of successive signals—which are separated from one another by more than one period of a reference clock signal—by recording the number of nodes disposed within a plurality of fine delay paths—each coupled to a different one of a plurality of coarse delay stages in a first coarse delay path—through which the signals propagate. The delay across each fine delay path is substantially the same as the delay across a coarse delay stage in the coarse delay path. A phase detector maintains the clock signal and its delayed replica in phase by adjusting the delay through each of the coarse delay stages in a second coarse delay path. The time delay between the clock signal and its delayed replica is equal to one period of the clock signal.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: December 31, 2002
    Inventor: Burnell G. West
  • Publication number: 20020188902
    Abstract: Testing an integrated circuit (IC) device, for example, an IC that includes an embedded memory, may involve specifying one or more test parameters including at least one of a pipeline depth data (e.g., latency delay information) and a data width data (e.g. corresponding to a data width of an embedded memory), generating a test sequence by associating test parameters with a test pattern, and applying the generated test sequence to the integrated circuit device. A test system for testing ICs having embedded memories may include multiple test patterns and multiple data structures, each data structure defining one or more test parameters including at least one of a pipeline depth and a data width, an algorithmic pattern generator, and software for controlling the algorithmic pattern generator to generate a test sequence by associating a specified data structure with a specified test pattern.
    Type: Application
    Filed: March 19, 2002
    Publication date: December 12, 2002
    Inventors: Daniel Fan, Kris Sakaitani, Burnell G. West
  • Patent number: 6285963
    Abstract: Apparatus and method for measuring the time interval between a first event and a second event in a tester system. First and second time measurement circuits independently receive respective first and second events. The time measurement circuits each includes a coarse counter clocked by the master clock. The first coarse counter is activated by an initial event, and the first coarse counter stops counting upon activation of the first event. The second coarse counter is also activated by the initial event, and the second coarse counter stops counting upon activation of the second event. A first fine counter clocked by the master clock produces a count value representing the time interval between the first event and a first leading edge of the master clock. A second fine counter clocked by the master clock produces a count value representing the time interval between the second event and a second leading edge of the master clock.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: September 4, 2001
    Assignee: Schlumberger Technologies, Inc.
    Inventor: Burnell G. West
  • Patent number: 6128754
    Abstract: In a tester for testing circuits, apparatus and methods for acquiring waveform data from a circuit under test. While a test program is being run by the tester, waveform acquisition strobe events are generated for application to a terminal of a circuit under test. A measurement circuit receives the waveform acquisition strobe events and applies each strobe event to the terminal of the circuit and generates result signals representing the result of applying the strobe events to the terminal. A capture memory receives and stores result signals generated by the measurement circuit.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: October 3, 2000
    Assignee: Schlumberger Technologies, Inc.
    Inventors: Egbert Graeve, Burnell G. West
  • Patent number: 6081484
    Abstract: Apparatus and method for measuring the time interval between a first event and a second event in a tester system. First and second time measurement circuits independently receive respective first and second events. The time measurement circuits each includes a coarse counter clocked by the master clock. The first coarse counter is activated by an initial event, and the first coarse counter stops counting upon activation of the first event. The second coarse counter is also activated by the initial event, and the second coarse counter stops counting upon activation of the second event. A first fine counter clocked by the master clock produces a count value representing the time interval between the first event and a first leading edge of the master clock. A second fine counter clocked by the master clock produces a count value representing the time interval between the second event and a second leading edge of the master clock.
    Type: Grant
    Filed: October 14, 1997
    Date of Patent: June 27, 2000
    Assignee: Schlumberger Technologies, Inc.
    Inventor: Burnell G. West
  • Patent number: 6025736
    Abstract: A high speed active link switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed. An advantage of the active link technology disclosed herein is that the active links do not degrade rise and fall times of high speed data signals nearly as much as the passive links of prior art field programmable gate arrays thereby enabling use of FPGAs in higher speed applications than was previously possible.
    Type: Grant
    Filed: June 4, 1997
    Date of Patent: February 15, 2000
    Assignee: Dynalogic
    Inventors: Madhukar Vora, Burnell G. West
  • Patent number: 6014764
    Abstract: Apparatus and methods providing pattern chaining and looping in a circuit tester. The tester has a pattern data memory for storing multiple patterns and for storing a pattern chaining definition. Each pattern has pattern data for one or more test vectors. The pattern chaining definition specifies (i) a sequential order for the patterns and (ii) a location in the pattern data memory of each of the patterns. When the tester executes a functional test, the pattern chaining definition is read from the pattern data memory and used to locate each of the patterns, and the pattern data of each pattern is read to provide a test vector for each test period of the functional test. In another aspect, both a pattern program including one or more test vectors and a loop definition are stored in the pattern data memory. The pattern program defines an ordering for the test vectors, and the loop definition specifies a loop of test vectors.
    Type: Grant
    Filed: May 20, 1997
    Date of Patent: January 11, 2000
    Assignee: Schlumberger Technologies Inc.
    Inventors: Egbert Graeve, Burnell G. West, Teck Chiau Chew
  • Patent number: 6002268
    Abstract: An interface circuit for use in the layout of padframe interface circuits for field programmable gate arrays having a plurality of I/O cells each of which may be programmed as an input or an output (or both) and a programmable connection matrix which provide programmable pathways between the data output signals generated by the core array of logic blocks and I/O cells programmed as outputs and provide programmable pathways between I/O cells programmed as inputs and data input conductors going into the core array. The interface circuits are all substantially identical in structure, and each includes a sufficient number of power and ground connections to supply adequate current to the number of I/O cells the interface has. Each interface circuit also includes at least one and preferably two open spaces into which conductive paths may be laid out to carry power to the core array or carry dedicated signals to circuits other than the core which also reside on the integrated circuit.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: December 14, 1999
    Assignee: DynaChip Corporation
    Inventors: Paul Takao Sasaki, Madhukar Vora, Burnell G West
  • Patent number: 5668495
    Abstract: A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.
    Type: Grant
    Filed: April 23, 1996
    Date of Patent: September 16, 1997
    Assignee: DynaChip Corporation
    Inventors: Madhukar B. Vora, Burnell G. West
  • Patent number: 5570059
    Abstract: A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.
    Type: Grant
    Filed: January 20, 1995
    Date of Patent: October 29, 1996
    Assignee: Dyna Logic Corporation
    Inventors: Madhukar B. Vora, Burnell G. West
  • Patent number: 5475624
    Abstract: Generation, validation and fault-grading of test patterns, and test and debug of logic circuits, are enhanced by emulation of the logic circuits in programmable gate arrays. Two emulations of the logic circuit are preferably created, one of which is a "good" model containing no faults and the other of which is a "faultable" model into which possible faults may be selectively introduced. A fault is introduced in the faultable model, and the two models are exercised in parallel by applying the same pattern of test vectors to both models. The test vector pattern may be generated by an emulation of the intended operating environment of the logic circuit. Differences in the output signals of the two models indicate that the fault has been detected by the applied test pattern. Application of the test pattern is repeated for each of a sequence of possible faults, to determine the extent to which the test pattern enables detection of faults in the logic circuit.
    Type: Grant
    Filed: April 30, 1992
    Date of Patent: December 12, 1995
    Assignee: Schlumberger Technologies, Inc.
    Inventor: Burnell G. West
  • Patent number: 5430400
    Abstract: Driver circuits are provided which also serve as termination and clamp in an IC tester. When it is to drive a port of a device under test (DUT) between two predetermined voltage levels, the driver's I/O terminal is switched between two predetermined voltage levels with an output impedance that matches the transmission line between the driver circuit and the DUT. When the DUT's port is supplying an output signal, the driver circuit can be programmed to provide one of two types of termination. If the DUT's port is specified as capable of driving the load, the transmission line between the driver circuit and the DUT is terminated by switching the driver circuit's I/O terminal to a predetermined voltage level with an impedance of Z.sub.0. If the DUT's port is not specified as being capable of driving such a termination load, the driver circuit functions like a Z-clamp circuit.
    Type: Grant
    Filed: August 3, 1993
    Date of Patent: July 4, 1995
    Assignee: Schlumberger Technologies Inc.
    Inventors: Richard F. Herlein, Sergio A. Sanielevici, Burnell G. West, David K. Cheung
  • Patent number: 5406133
    Abstract: A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: April 11, 1995
    Assignee: Dyna Logic Corporation
    Inventors: Madhukar B. Vora, Burnell G. West
  • Patent number: 5397943
    Abstract: There is disclosed herein a method and apparatus for distributing high speed clock signals on an integrated circuit while eliminating clock skew. The invention is particularly useful in field programmable gate arrays where the signal paths are defined by the user after the integrated circuit leaves the place of manufacture and enables field programmable gate arrays to operate at clock speeds in excess of 200 MHz, a speed not previously attainable. Clock skew is eliminated by generating differential clock signals at each of four corners of the array from master differential clock signal delivered simultaneously to each of the four corners. The differential clock signals generated at each corner have ramps the rise time of which slightly exceeds the propagation delay of a clock signal traversing the array.
    Type: Grant
    Filed: July 8, 1993
    Date of Patent: March 14, 1995
    Assignee: Dyna Logic Corporation
    Inventors: Burnell G. West, Madhukar B. Vora