Burnell G. West has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A high speed switching technology suitable for implementing field programmable gate arrays using current mode logic in the high speed data path, and CMOS steering logic outside the high speed data path to enable the high speed switching logic and to implement multiplexer, selector and crossbar switch functions. High speed emitter follower logic compatible with the high speed switching logic for level shifting, buffering, and providing more current sink or source capacity is also disclosed.
Abstract: A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connects the timing signals to timing generators 20. A central processing unit 28 supplies data to the period generators and timing generators to define their respective timing signals. Timing signals generated by the major period generator 12 define the overall testing rate. The minor period generator 14 generates multiple timing signals within the periods of the major clock signals to permit higher clock rates. Timing signals that are independent of the major clock periods are generated by the free-run period generator 16. An external synchronizer circuit 26 provides a feedback loop from the device under test 22 to the major period generator. A reference driver trigger delay circuit 27 provides means for calibrating the timing generators.
Abstract: An electrical pulse edge timing adjustment circuit 10 comprising one or more deskew elements 5. In each deskew element, a pulse train is passed through an inverter 20. The falling rate of pulse edges on the inverter output line 21 is controlled by a capacitor 24 and an adjustable current sink 25 which determine the output line capacitance discharge rate. From the output line, pulses are passed to another deskew element which re-inverts the pulses and delays the formerly rising pulse edges. Each current sink is independently adjustable to allow different delays in the rising and falling edges.
December 23, 1982
Date of Patent:
October 29, 1985
Fairchild Camera and Instrument Corporation
Abstract: A closed loop integrated circuit temperature stabilizer 10 has an on-chip temperature sensor 12 for supplying a voltage indication of temperature to an op amp 22 which maintains chip temperature equilibrium by controlling a load transistor 30 which draws current through on-chip heating means 16.