Patents by Inventor Byeong-Chan Lee

Byeong-Chan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10008600
    Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: June 26, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam Kyu Kim, Dong Chan Suh, Kwan Heum Lee, Byeong Chan Lee, Cho Eun Lee, Su Jin Jung, Gyeom Kim, Ji Eon Yoon
  • Patent number: 9972716
    Abstract: Provided are semiconductor devices that include an active pattern on a substrate, first and second gate electrodes on the active pattern and arranged in a first direction relative to one another and a first source/drain region in a first trench that extends into the active pattern between the first and second gate electrodes. The first source/drain region includes a first epitaxial layer that is configured to fill the first trench and that includes at least one plane defect that originates at a top portion of the first epitaxial layer and extends towards a bottom portion of the first epitaxial layer.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: May 15, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Bum Kim, Seok-Hoon Kim, Chul Kim, Kwan-Heum Lee, Byeong-Chan Lee, Cho-Eun Lee, Su-Jin Jung, Bon-Young Koo
  • Patent number: 9881838
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: January 30, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon Hae Kim, Jin Wook Lee, Jong Ki Jung, Myung Il Kang, Kwang Yong Yang, Kwan Heum Lee, Byeong Chan Lee
  • Publication number: 20170352759
    Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.
    Type: Application
    Filed: August 24, 2017
    Publication date: December 7, 2017
    Inventors: Nam Kyu KIM, Dong Chan SUH, Kwan Heum LEE, Byeong Chan LEE, Cho Eun LEE, Su Jin JUNG, Gyeom KIM, Ji Eon YOON
  • Publication number: 20170317081
    Abstract: A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.
    Type: Application
    Filed: July 19, 2017
    Publication date: November 2, 2017
    Inventors: SEOK-HOON KIM, JIN-BUM KIM, KWAN-HEUM LEE, BYEONG-CHAN LEE, CHO-EUN LEE, JIN-HEE HAN, BON-YOUNG KOO
  • Patent number: 9806800
    Abstract: An Ethernet-based optical transmission system, and particularly, an apparatus and method for controlling a remote optical Ethernet device. An optical Ethernet apparatus includes a system recovery processor configured to output a system reset signal or a system power ON/OFF control signal and a system recovery controller configured to detect a system recovery command that occurs when a predetermined signal pattern is repeated the designated number of times for a designated period of time, and to control the system recovery processor using the detected system recovery command.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: October 31, 2017
    Assignees: DASAN Networks, Inc., DASAN Network Solutions, Inc.
    Inventors: Sang Cheol Mun, Byeong Chan Lee
  • Patent number: 9793356
    Abstract: A semiconductor device may have a structure that prevents or reduces an etching amount of certain portions, such as a part of a source/drain region. Adjacent active fins may be merged with a blocking layer extending between adjacent the source/drain region. The blocking layer may be of a material that is relatively high-resistant to the etchant.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: October 17, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Ho Yoo, Byeong-Chan Lee, Hyun-Ho Noh, Yong-Kook Park, Bon-Young Koo, Jin-Yeong Joe
  • Patent number: 9761719
    Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: September 12, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam Kyu Kim, Dong Chan Suh, Kwan Heum Lee, Byeong Chan Lee, Cho Eun Lee, Su Jin Jung, Gyeom Kim, Ji Eon Yoon
  • Patent number: 9755076
    Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-hoon Kim, Jin-bum Kim, Kwan-heum Lee, Byeong-chan Lee, Cho-eun Lee, Su-jin Jung
  • Patent number: 9735158
    Abstract: A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: August 15, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Hoon Kim, Jin-Bum Kim, Kwan-Heum Lee, Byeong-Chan Lee, Cho-Eun Lee, Jin-Hee Han, Bon-Young Koo
  • Publication number: 20170195042
    Abstract: An Ethernet-based optical transmission system, and particularly, an apparatus and method for controlling a remote optical Ethernet device. An optical Ethernet apparatus includes a system recovery processor configured to output a system reset signal or a system power ON/OFF control signal and a system recovery controller configured to detect a system recovery command that occurs when a predetermined signal pattern is repeated the designated number of times for a designated period of time, and to control the system recovery processor using the detected system recovery command.
    Type: Application
    Filed: January 22, 2016
    Publication date: July 6, 2017
    Applicants: DASAN Networks, Inc, DASAN Network Solutions, Inc.
    Inventors: Sang Cheol Mun, Byeong Chan Lee
  • Publication number: 20170133275
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.
    Type: Application
    Filed: January 24, 2017
    Publication date: May 11, 2017
    Inventors: Yoon Hae KIM, Jin Wook LEE, Jong Ki JUNG, Myung II KANG, Kwang Yong YANG, Kwan Heum LEE, Byeong Chan LEE
  • Publication number: 20170117406
    Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.
    Type: Application
    Filed: January 5, 2017
    Publication date: April 27, 2017
    Inventors: Seok-Hoon KIM, Bon-Young KOO, Nam-Kyu KIM, Woo-Bin SONG, Byeong-Chan LEE, Su-Jin JUNG
  • Publication number: 20170092766
    Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer.
    Type: Application
    Filed: December 14, 2016
    Publication date: March 30, 2017
    Inventors: Seok-hoon KIM, Jin-bum Kim, Kwan-heum Lee, Byeong-chan Lee, Cho-eun Lee, Su-jin Jung
  • Patent number: 9608117
    Abstract: A semiconductor device includes an active fin structure extending in a first direction, the active fin structure including protruding portions divided by a recess, a plurality of gate structures extending in a second direction crossing the first direction and covering the protruding portions of the active fin structure, a first epitaxial pattern in a lower portion of the recess between the gate structures, a second epitaxial pattern on a portion of the first epitaxial pattern, the second epitaxial pattern contacting a sidewall of the recess, and a third epitaxial pattern on the first and second epitaxial patterns, the third epitaxial pattern filling the recess.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: March 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Bum Kim, Nam Kyu Kim, Hyun-Ho Noh, Dong-Chan Suh, Byeong-Chan Lee, Su-Jin Jung, Jin-Yeong Joe, Bon-Young Koo
  • Patent number: 9595611
    Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.
    Type: Grant
    Filed: April 26, 2014
    Date of Patent: March 14, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok-Hoon Kim, Bon-Young Koo, Nam-Kyu Kim, Woo-Bin Song, Byeong-Chan Lee, Su-Jin Jung
  • Patent number: 9590103
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: March 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon Hae Kim, Jin Wook Lee, Jong Ki Jung, Myung II Kang, Kwang Yong Yang, Kwan Heum Lee, Byeong Chan Lee
  • Patent number: 9553192
    Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: January 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-hoon Kim, Jin-bum Kim, Kwan-heum Lee, Byeong-chan Lee, Cho-eun Lee, Su-jin Jung
  • Publication number: 20160343858
    Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.
    Type: Application
    Filed: January 8, 2016
    Publication date: November 24, 2016
    Inventors: Yoon Hae KIM, Jin Wook LEE, Jong Ki JUNG, Myung II KANG, Kwang Yong YANG, Kwan Heum LEE, Byeong Chan LEE
  • Publication number: 20160308052
    Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer.
    Type: Application
    Filed: June 22, 2016
    Publication date: October 20, 2016
    Inventors: Seok-hoon Kim, Jin-bum Kim, Kwan-heum Lee, Byeong-chan Lee, Cho-eun Lee, Su-jin Jung