Abstract: In one embodiment, a method for fabricating a semiconductor package includes providing a multi-layer molded conductive structure. The multi-layer molded conductive structure includes a first conductive structure disposed on a surface of a carrier and a first encapsulant covering at least portions of the first conductive structure while other portions are exposed in the first encapsulant. A second conductive structure is disposed on the first encapsulant and electrically connected to the first conductive structure. A second encapsulant covers a first portion of the second conductive structure while a second portion of the second conductive structure is exposed to the outside, and a third portion of the second conductive structure is exposed in a receiving space disposed in the second encapsulant. The method includes electrically connecting a semiconductor die to the second conductive structure and in some embodiments removing the carrier.

Abstract: In one embodiment, an electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns and a package body encapsulating the top surface of the insulating material and the electronic device, wherein the bottom land surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer.

Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices made thereby, that utilize a film assist mold process.

Abstract: In one embodiment, a semiconductor device includes a single layer substrate having an insulation layer and conductive patterns on a first surface of the insulation layer. A semiconductor die is attached on a first surface of the single layer substrate and electrically connected to the conductive patterns. Conductive bumps are also on the first surface of the single layer substrate and electrically connected to the semiconductor die through the conductive patterns. An encapsulant overlaps at least portions of the first surface of the single layer substrate. The conductive bumps are at least partially exposed in the encapsulant.

Abstract: A semiconductor package, and a method of manufacturing thereof, comprising a contact in a plated sidewall encapsulant opening, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

Abstract: A semiconductor package includes a first package comprising a circuit board and a first semiconductor die mounded on the circuit board, and a second package comprising a mounting board. At least one second semiconductor die may be mounted on the mounting board, and one or more leads may be electrically connected to the mounting board and/or the second semiconductor die. An adhesion member may bond the first package to the second package, and an encapsulant may encapsulate the first package and the second package. the circuit board, the mounting board, and the one or more leads may be arranged to surround the first semiconductor die and the second semiconductor die, and the plurality of leads may be electrically connected to the circuit board and to a constant potential or ground, to reduce the effects of external electromagnetic interference upon the semiconductor package.

Abstract: In one embodiment, an electronic package includes a substrate having a die pad plurality of lands embedded within substrate encapsulant. An electronic chip including an electronic component is connected to the die pad. The die pad is configured with a recessed well extending from a top surface of the die pad towards a bottom surface of the die pad. The electronic component is position at least proximate to and overlapping the recessed well to increase the distance between the die pad and the electronic component. In one embodiment, the electronic component includes a passive component, such as an inductor. A package body encapsulates the electronic chip and top surfaces of the substrate, and is further disposed within the recessed well. The die pad bottom surface is continuous below the recessed well.

Abstract: A selectively shielded and/or three-dimensional semiconductor device and a method of manufacturing thereof. For example and without limitation, various aspects of this disclosure provide a semiconductor device that comprises a composite plate for selective shielding and/or a three-dimensional embedded component configuration.

Abstract: In one embodiment, a method for forming a package substrate includes selectively removing portions of a lead frame to form cavities and filling the cavities with a resin layer to define an adhesion pad and a land structure. Top portions of the lead frame are selectively removed to isolate the adhesion pad and the land structure from each other, to expose a top surface of the resin layer, and to form at least one land having a part with a relatively greater size than the size of a respective lower part.

Abstract: In one embodiment, an electronic package structure includes a lead having a first width. An electronic chip having a conductive bump on a major surface, the conductive bump has a second width greater than the first width. The conductive bump is attached to the lead such that a portion of the conductive bump extends to at least partially surround a side surface of the lead. A molding compound resin encapsulates the electronic chip, the conductive bump, and at least a portion of the lead. The lead is configured so strengthen the joining force between the lead and conductive bump.

Abstract: In one embodiment, a method for forming a package substrate includes selectively removing portions of a lead frame to form cavities and filling the cavities with a resin layer to define an adhesion pad and a land structure. Top portions of the lead frame are selectively removed to isolate the adhesion pad and the land structure from each other, to expose a top surface of the resin layer, and to form at least one land having a part with a relatively greater size than the size of a respective lower part.

Abstract: In one embodiment, a semiconductor device includes a die pad defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads and lands which are provided in a prescribed arrangement. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads and lands. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the lands being exposed in a common exterior surface of the package body.

Abstract: In one embodiment, a semiconductor device includes a single layer substrate having an insulation layer and conductive patterns on a first surface of the insulation layer. A semiconductor die is attached on a first surface of the single layer substrate and electrically connected to the conductive patterns. Conductive bumps are also on the first surface of the single layer substrate and electrically connected to the semiconductor die through the conductive patterns. An encapsulant overlaps at least portions of the first surface of the single layer substrate. The conductive bumps are at least partially exposed in the encapsulant.

Abstract: A semiconductor device with fine pitch redistribution layers is disclosed and may include a semiconductor die with a bond pad and a first passivation layer comprising an opening above the bond pad. A redistribution layer (RDL) may be formed on the passivation layer with one end of the RDL electrically coupled to the bond pad and a second end comprising a connection region. A second passivation layer may be formed on the RDL with an opening for the connection region of the RDL. An under bump metal (UBM) may be formed on the connection region of the RDL and a portion of the second passivation layer. A bump contact may be formed on the UBM, wherein a width of the RDL is less than a width of the opening in the second passivation layer and may be constant from the bond pad through at least a portion of the opening.

Abstract: In one embodiment, a micro lead frame structure includes one or more stiffness reinforcing structures formed on leads and/or connecting structures. The stiffness reinforcing structures can be formed by leaving predetermined portions of the micro lead frame at full thickness including, for example, portions of an inner lead, portions of an outer lead, and portions of a connecting bar, combinations thereof, and other structures. The stiffness reinforcing structures are configured to reduce deformation defects and electrical short defects caused by assembly processes.

Abstract: In one embodiment, a method for forming an electronic package structure includes providing a single unit leadframe having first terminals on a first or top surface. An electronic device is attached to the single unit leadframe and electrically connected to the first terminals. The leadframe, first terminals, and the electronic device are encapsulated with an encapsulating material. Second terminals are then formed by removing portions of a second or bottom surface of the leadframe. In one embodiment, the method can be used to fabricate a thin substrate chip scale package (“tsCSP”) type structure.

Abstract: In one embodiment, an electronic package structure includes a lead having a first width. An electronic chip having a conductive bump on a major surface, the conductive bump has a second width greater than the first width. The conductive bump is attached to the lead such that a portion of the conductive bump extends to at least partially surround a side surface of the lead. A molding compound resin encapsulates the electronic chip, the conductive bump, and at least a portion of the lead. The lead is configured so strengthen the joining force between the lead and conductive bump.

Abstract: In one embodiment, a micro lead frame structure includes one or more stiffness reinforcing structures formed on leads and/or connecting structures. The stiffness reinforcing structures can be formed by leaving predetermined portions of the micro lead frame at full thickness including, for example, portions of an inner lead, portions of an outer lead, and portions of a connecting bar, combinations thereof, and other structures. The stiffness reinforcing structures are configured to reduce deformation defects and electrical short defects caused by assembly processes.

Abstract: Methods and devices for a semiconductor device having conductive pads to prevent solder reflow are disclosed and may include a substrate comprising conductive pads of rectangular shape and neck-down portions on opposite sides of the rectangular shape, a semiconductor die comprising conductive pillars, and a solder electrically coupling the conductive pillars to the conductive pads. The neck-down portions may comprise a solder mask for the conductive pads to prevent solder from flowing in an unwanted direction on the conductive pads. The conductive pillars may comprise an elliptical cross-section with a minor axis length X and a major axis length Y. The major axis of the elliptical cross-section may be parallel to a long axis of the rectangular shape of the conductive pads. A decrease (W) in width of the conductive pads from the rectangular shape to the neck-down portions may be defined by X/5?W?X/2.

Abstract: In one embodiment, a lead frame package structure includes a lead frame having sides that surround a die paddle and on which a plurality of leads are formed. An electronic chip is attached to the die paddle and a case is attached to the lead frame to seal the leads and the electronic chip. One or more discharge holes are formed on and extending through one or more specific leads and/or on and extending through a predetermined position of the die paddle. The discharge holes are configured to discharge air pressure that forms during the assembly process thereby improving the reliability of the packaged electronic chip.