Abstract: The present disclosure relates to a method for extracting caffeic acid and rosmarinic acid from Rosmarinus officinalis L., and more particularly, to a method for extracting caffeic acid and rosmarinic acid from Rosmarinus officinalis L., the method comprising the steps of: (S1) preparing an extraction apparatus including an extractor for passing a solution contained in a main body unit through a filtration membrane to obtain a filtered solution, and dropping the filtered solution to the lower outside through a dropping unit connected to a lower portion of the main body unit, and a receiver located in the lower part of the extractor to collect the filtered solution that is dropped from the dropping unit; (S2) putting dried Rosmarinus officinalis L. into the main body unit, and adding a solvent to the main body unit to immerse the dried Rosmarinus officinalis L. at room temperature; and (S3) dropping a solution in which the dried Rosmarinus officinalis L.

Abstract: The present invention relates to a monoclonal antibody specifically recognizing a spike protein of MERS coronavirus (MERS-CoV) or a part of the protein, or a functional fragment thereof, wherein the monoclonal antibody, or functional fragment of the monoclonal antibody characterized in that it comprises polypeptide sequence selected from the group consisting of the following polypeptide sequences: a heavy chain comprising a complementarity determining region 1 (CDR 1) amino acid sequence consisting of the sequence of SEQ ID NO: 1, a CDR2 consisting of the sequence of SEQ ID NO: 2 and a CDR 3 consisting of the sequence of SEQ ID NO: 3; and a light chain comprising CDR1 amino acid sequence consisting of the sequence of SEQ ID NO: 4, a CDR2 consisting of the sequence of SEQ ID NO: 5 and a CDR 3 consisting of the sequence of SEQ ID NO: 6. and uses thereof.

Abstract: The present invention relates to: a therapeutic composition for coronavirus comprising, as an active ingredient, one peptide selected from the group consisting of SEQ ID NO: 1, SEQ ID NO: 6, and SEQ ID NO: 8 that binds to a coronavirus N-protein, a coronavirus-derived spike protein, or a fragment of the spike protein; and a composition that binds to a coronavirus N-protein comprising, as an active ingredient, the coronavirus-derived spike protein or the fragment of the spike protein. It is suggested that the peptides of the present invention, based on the understanding and targeting of the interaction of the coronavirus S protein and N protein of the present invention, have an effect that can be helpful in the treatment of coronaviruses including MERS-CoV, SARS-CoV-2, SARS-CoV, and HCoV-OC43.

Abstract: The present disclosure relates to a composition that is capable of preventing hair loss and promoting hair growth by comprising the extract of the above-ground part of carrots. The composition comprising the extract of the above-ground part of carrots of the present disclosure significantly increases the viability of dermal papilla cells and can inhibit the expression of 5a-reductase, thereby exhibiting excellent effects in preventing hair loss and promoting hair growth.

Abstract: The present disclosure relates to a moisturizing or anti-atopic composition, including a fatty acid or a fatty acid derivative. More specifically, the present disclosure relates to a moisturizing or anti-atopic composition including at least one compound selected from the group consisting of ethyl linoleate, ?-linolenic acid, and monolinolein as an active ingredient. The composition for moisturizing or anti-atopic dermatitis, according to the present disclosure, has not only low cytotoxicity but also an anti-inflammatory effect, an increase in the amount of moisturizing factor production, an increase in the amount of skin bather strengthening factor production, and an active effect to inhibit the production of atopic factors, so it can be used in various fields such as beauty for improving skin condition, pharmaceuticals, and food.

Abstract: The present disclosure provides a fragrant material composition and cosmetic composition comprising Rosmarinus officinalis essential oil and Torreya nucifera leaf essential oil as active ingredients, wherein the Rosmarinus officinalis essential oil contains ?-pinene and verbenone, and the fragrant material composition and cosmetic composition can be variously used in such fields as beauty and cosmetics by having effects of helping in stress relief and calming, tension relief, emotional stability, and mind and body stability.

Abstract: The present disclosure relates to a method for extracting caffeic acid and rosmarinic acid from Rosmarinus officinalis L., and more particularly, to a method for extracting caffeic acid and rosmarinic acid from Rosmarinus officinalis L., the method comprising the steps of: (S1) preparing an extraction apparatus including an extractor for passing a solution contained in a main body unit through a filtration membrane to obtain a filtered solution, and dropping the filtered solution to the lower outside through a dropping unit connected to a lower portion of the main body unit, and a receiver located in the lower part of the extractor to collect the filtered solution that is dropped from the dropping unit; (S2) putting dried Rosmarinus officinalis L. into the main body unit, and adding a solvent to the main body unit to immerse the dried Rosmarinus officinalis L. at room temperature; and (S3) dropping a solution in which the dried Rosmarinus officinalis L.

Abstract: The present invention relates to a monoclonal antibody specifically recognizing a spike protein of MERS coronavirus (MERS-CoV) or a part of the protein, or a functional fragment thereof, wherein the monoclonal antibody, or functional fragment of the monoclonal antibody characterized in that it comprises polypeptide sequence selected from the group consisting of the following polypeptide sequences: a heavy chain comprising a complementarity determining region 1(CDR 1) amino acid sequence consisting of the sequence of SEQ ID NO: 1, a CDR2 consisting of the sequence of SEQ ID NO: 2 and a CDR 3 consisting of the sequence of SEQ ID NO: 3; and a light chain comprising CDR1 amino acid sequence consisting of the sequence of SEQ ID NO: 4, a CDR2 consisting of the sequence of SEQ ID NO: 5 and a CDR 3 consisting of the sequence of SEQ ID NO: 6.and uses thereof.

Abstract: A semiconductor memory may include: a bank control signal generation unit suitable for sequentially generating a plurality of bank control signals for controlling a memory bank based on an active command, a signal detection unit suitable for detecting a firstly activated signal and a lastly activated signal among the bank control signals, and a bank enable control unit suitable for controlling an active period of the memory bank in response to the detected signals.

Abstract: A semiconductor memory may include: a bank control signal generation unit suitable for sequentially generating a plurality of bank control signals for controlling a memory bank based on an active command, a signal detection unit suitable for detecting a firstly activated signal and a lastly activated signal among the bank control signals, and a bank enable control unit suitable for controlling an active period of the memory bank in response to the detected signals.

Abstract: A system for controlling a refresh operation of a plurality of stacked semiconductor chips includes a first semiconductor configured to output a refresh signal for performing a refresh operation, and a semiconductor chip discrimination signal, and a plurality of second semiconductor chips configured to perform a refresh operation at different timings in response to the refresh signal, and the semiconductor chip discrimination signal.

Abstract: A system for controlling a refresh operation of a plurality of stacked semiconductor chips includes a first semiconductor configured to output a refresh signal for performing a refresh operation, and a semiconductor chip discrimination signal, and a plurality of second semiconductor chips configured to perform a refresh operation at different timings in response to the refresh signal, and the semiconductor chip discrimination signal.

Abstract: Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a redundancy signal generation unit configured to compare mat information set by fuse cutting with address information inputted from outside and generate a plurality of redundancy signals; a mat designation signal generation unit configured to generate a plurality of mat designation signals in response to the plurality of redundancy signals and a plurality of mat address signals; and a mat control signal generation group configured to enable one of the mat control signals in response to the plurality of mat designation signals.

Abstract: Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a redundancy signal generation unit configured to compare mat information set by fuse cutting with address information inputted from outside and generate a plurality of redundancy signals; a mat designation signal generation unit configured to generate a plurality of mat designation signals in response to the plurality of redundancy signals and a plurality of mat address signals; and a mat control signal generation group configured to enable one of the mat control signals in response to the plurality of mat designation signals.

Abstract: A semiconductor integrated circuit includes a semiconductor chip including a memory cell array, a plurality of first through-chip vias configured to vertically penetrate through the semiconductor chip and operate as an interface for a signal and a supply voltage, and a semiconductor substrate. The semiconductor substrate includes a peripheral circuit region coupled to the plurality of first through-chip vias and configured to control the semiconductor chip and a conductivity pattern region configured to operate as an interface for the signal and the supply voltage between the peripheral circuit region and an external controller.

Abstract: A system for controlling a refresh operation of a plurality of stacked semiconductor chips includes a first semiconductor configured to output a refresh signal for performing a refresh operation, and a semiconductor chip discrimination signal, and a plurality of second semiconductor chips configured to perform a refresh operation at different timings in response to the refresh signal, and the semiconductor chip discrimination signal.

Abstract: The semiconductor memory testing device includes a test signal decoder decoding burn-in test mode signals which generates a first test signal for use in controlling entire main wordlines and which generates a second test signal for use in controlling sub wordlines. When the first and second test signals are in an disabled state, the semiconductor memory testing device also includes a plurality of bank control units generating a multi wordline test mode signal as a multi wordline test signal corresponding to a bank control signal, and simultaneously enabling a plurality of wordlines in accordance to the multi wordline test signal to perform a test. The semiconductor memory testing device reduces a testing time and current consumption and thus enhances a more stable voltage drop when performing continuous multi wordline test on a per bank basis.

Abstract: A charge storage circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to a corresponding word line among the word lines and connected to a corresponding bit line among the bit lines. Each of the memory cells includes a transistor turned on in response to a predetermined voltage of the corresponding word line and connected to the corresponding bit line, and a capacitor having one end connected to the transistor and the other end connected to the corresponding word line.

Abstract: The semiconductor memory testing device includes a test signal decoder decoding burn-in test mode signals which generates a first test signal for use in controlling entire main wordlines and which generates a second test signal for use in controlling sub wordlines. When the first and second test signals are in an disabled state, the semiconductor memory testing device also includes a plurality of bank control units generating a multi wordline test mode signal as a multi wordline test signal corresponding to a bank control signal, and simultaneously enabling a plurality of wordlines in accordance to the multi wordline test signal to perform a test. The semiconductor memory testing device reduces a testing time and current consumption and thus enhances a more stable voltage drop when performing continuous multi wordline test on a per bank basis.

Abstract: The semiconductor memory testing device includes a test signal decoder decoding burn-in test mode signals which generates a first test signal for use in controlling entire main wordlines and which generates a second test signal for use in controlling sub wordlines. When the first and second test signals are in an disabled state, the semiconductor memory testing device also includes a plurality of bank control units generating a multi wordline test mode signal as a multi wordline test signal corresponding to a bank control signal, and simultaneously enabling a plurality of wordlines in accordance to the multi wordline test signal to perform a test. The semiconductor memory testing device reduces a testing time and current consumption and thus enhances a more stable voltage drop when performing continuous multi wordline test on a per bank basis.