Patents by Inventor Byoung W. Min
Byoung W. Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9299856Abstract: Fluorine is located in selective portions of a gate oxide to adjust characteristics of the gate oxide. In some embodiments, the fluorine promotes oxidation which increases the thickness of the selective portion of the gate oxide. In some embodiments, the fluorine lowers the dielectric constant of the oxide at the selective portion. In some examples, having fluorine at selective portions of a select gate oxide of a non volatile memory may reduce program disturb of the memory.Type: GrantFiled: February 10, 2015Date of Patent: March 29, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventor: Byoung W. Min
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Patent number: 9082650Abstract: A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A spacer select gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate. A dummy gate structure formed in a logic region has a dummy gate surrounded by an insulating layer. Performing chemical polishing results in the top surface of the charge storage layer being coplanar with top surface of the dummy gate structure. Replacing a portion of the dummy gate structure with a metal logic gate which includes a further chemical mechanical polishing results in the top surface of the charge storage layer being coplanar with the metal logic gate.Type: GrantFiled: August 21, 2013Date of Patent: July 14, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Asanga H. Perera, Cheong Min Hong, Sung-Taeg Kang, Byoung W. Min, Jane A. Yater
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Publication number: 20150179821Abstract: Fluorine is located in selective portions of a gate oxide to adjust characteristics of the gate oxide. In some embodiments, the fluorine promotes oxidation which increases the thickness of the selective portion of the gate oxide. In some embodiments, the fluorine lowers the dielectric constant of the oxide at the selective portion. In some examples, having fluorine at selective portions of a select gate oxide of a non volatile memory may reduce program disturb of the memory.Type: ApplicationFiled: February 10, 2015Publication date: June 25, 2015Inventor: BYOUNG W. MIN
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Patent number: 9059006Abstract: After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).Type: GrantFiled: June 14, 2012Date of Patent: June 16, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Satya N. Chakravarti, Dechao Guo, Chuck T. Le, Byoung W. Min, Thekkemadathil V. Rajeevakumar, Keith Kwong Hon Wong
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Patent number: 8975143Abstract: Fluorine is located in selective portions of a gate oxide to adjust characteristics of the gate oxide. In some embodiments, the fluorine promotes oxidation which increases the thickness of the selective portion of the gate oxide. In some embodiments, the fluorine lowers the dielectric constant of the oxide at the selective portion. In some examples, having fluorine at selective portions of a select gate oxide of a non volatile memory may reduce program disturb of the memory.Type: GrantFiled: April 29, 2013Date of Patent: March 10, 2015Assignee: Freescale Semiconductor, Inc.Inventor: Byoung W. Min
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Publication number: 20150054049Abstract: A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A spacer select gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate. A dummy gate structure formed in a logic region has a dummy gate surrounded by an insulating layer. Performing chemical polishing results in the top surface of the charge storage layer being coplanar with top surface of the dummy gate structure. Replacing a portion of the dummy gate structure with a metal logic gate which includes a further chemical mechanical polishing results in the top surface of the charge storage layer being coplanar with the metal logic gate.Type: ApplicationFiled: August 21, 2013Publication date: February 26, 2015Inventors: Asanga H. PERERA, Cheong Min HONG, Sung-Taeg KANG, Byoung W. MIN, Jane A. YATER
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Patent number: 8901632Abstract: A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM region and a first protection layer over a logic region. A control gate and a storage layer are formed over the substrate in the NVM region. The control gate has a top surface below a top surface of the select gate. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The first and second protection layers are removed from the logic region. A portion of the second protection layer is left over the control gate and the select gate. A gate structure, formed over the logic region, has a high k dielectric and a metal gate.Type: GrantFiled: September 30, 2013Date of Patent: December 2, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Asanga H. Perera, Cheong Min Hong, Sung-Taeg Kang, Byoung W. Min, Jane A. Yater
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Publication number: 20140319596Abstract: Fluorine is located in selective portions of a gate oxide to adjust characteristics of the gate oxide. In some embodiments, the fluorine promotes oxidation which increases the thickness of the selective portion of the gate oxide. In some embodiments, the fluorine lowers the dielectric constant of the oxide at the selective portion. In some examples, having fluorine at selective portions of a select gate oxide of a non volatile memory may reduce program disturb of the memory.Type: ApplicationFiled: April 29, 2013Publication date: October 30, 2014Inventor: Byoung W. Min
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Patent number: 8294239Abstract: An electrically programmable fuse (eFuse) comprises a semiconductor layer, a silicide layer overlying the semiconductor layer, and first and second contact structures electrically coupled to the silicide layer. The first contact structure is configured to function as an anode and the second contact structure is configured to function as a cathode. The eFuse further comprises a back-gate structure disposed underneath the semiconductor layer in a back-gate structure region proximate the second contact structure, the back-gate structure region excluding a region proximate the first contact structure.Type: GrantFiled: September 25, 2008Date of Patent: October 23, 2012Assignee: Freescale Semiconductor, Inc.Inventor: Byoung W. Min
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Publication number: 20120249160Abstract: After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).Type: ApplicationFiled: June 14, 2012Publication date: October 4, 2012Applicants: FREESCALE SEMICONDUCTOR, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Satya N. Chakravarti, Dechao Guo, Chuck T. Le, Byoung W. Min, Rajeevakumar V. Thekkemadathil, Keith Kwong Hon Wong
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Patent number: 8237457Abstract: After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).Type: GrantFiled: July 15, 2009Date of Patent: August 7, 2012Assignees: International Business Machines Corporation, Freescale Semiconductor, Inc.Inventors: Satya N. Chakravarti, Dechao Guo, Chuck T. Le, Byoung W. Min, Thekkemadathil V. Rajeevakumar, Keith Kwong Hon Wong
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Patent number: 8088657Abstract: An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).Type: GrantFiled: May 24, 2010Date of Patent: January 3, 2012Assignee: Freescale Semiconductor, Inc.Inventors: James D. Burnett, Leo Mathew, Byoung W. Min
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Patent number: 7927934Abstract: A method including providing a substrate and providing an insulating layer overlying the substrate is provided. The method further includes providing a body region comprising a body material overlying the insulating layer. The method further includes forming at least one transistor overlying the insulating layer, the at least one transistor having a source, a drain and a gate with a sidewall spacer, the sidewall spacer comprising a substantially uniform geometric shape around the gate, the gate overlying the body region. The method further includes forming a first silicide region within the source and a second silicide region within the drain, the first silicide region having a differing geometric shape than the second silicide region and being electrically conductive between the body region and the source.Type: GrantFiled: April 12, 2007Date of Patent: April 19, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Byoung W. Min, Dharmesh Jawarani
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Publication number: 20110012629Abstract: After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).Type: ApplicationFiled: July 15, 2009Publication date: January 20, 2011Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, FREESCALE SEMICONDUCTOR, INC.Inventors: Satya N. Chakravarti, Dechao Guo, Chuck T. Le, Byoung W. Min, Rajeevakumar V. Thekkemadathil, Keith Kwong Hon Wong
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Patent number: 7858505Abstract: A gate electrode is formed overlying a substrate. A first angled metal implant is performed at a first angle into the substrate followed by performing a second angled metal implant at a second angle. The first angled metal implant and the second angled metal implant form a first current electrode and a second current electrode. Each of the first current electrode and the second current electrode has at least two regions of differing metal composition. A metal layer is deposited overlying the gate electrode, the first current electrode and the second current electrode. The metal layer is annealed to form two Schottky junctions in each of the first current electrode and the second current electrode. The two Schottky junctions have differing barrier levels.Type: GrantFiled: May 4, 2007Date of Patent: December 28, 2010Assignee: Freescale Semiconductor, Inc.Inventor: Byoung W. Min
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Patent number: 7820530Abstract: A method for forming a body contacted SOI transistor includes forming a semiconductor layer (103) having a body contact region (120), a body access region (121), and an active region (122). An SOI transistor is formed in the active region by etching a metal gate structure (107, 108) to have a first portion (130) formed over the active region, and a second portion (131) formed over at least part of the body access region. By implanting ions (203, 301) at a non-perpendicular angle into an implant region (204, 302) in the body access region so as to encroach toward the active region and/or under the second portion of the etched metal gate structure, silicide (306) may be subsequently formed over the body contact region and the implant region, thereby reducing formation of a depletion region (308) in the body access region.Type: GrantFiled: October 1, 2008Date of Patent: October 26, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Byoung W. Min, Stefan Zollner, Qingqing Liang
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Publication number: 20100230762Abstract: An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).Type: ApplicationFiled: May 24, 2010Publication date: September 16, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: James D. Burnett, Leo Mathew, Byoung W. Min
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Patent number: 7754560Abstract: An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).Type: GrantFiled: January 10, 2006Date of Patent: July 13, 2010Assignee: Freescale Semiconductor, Inc.Inventors: James D. Burnett, Leo Mathew, Byoung W. Min
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Patent number: 7709303Abstract: A process for forming an electronic device can include forming a semiconductor fin of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin is shortened to a second height. In accordance with specific embodiment a second semiconductor fin can be formed, each of the first and the second semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second and a third semiconductor fin can be formed, each of the first, the second and the third semiconductor fins having a different height representing a channel width.Type: GrantFiled: January 10, 2006Date of Patent: May 4, 2010Assignee: Freescale Semiconductor, Inc.Inventors: James D. Burnett, Leo Mathew, Byoung W. Min
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Publication number: 20100078727Abstract: A semiconductor fabrication process and apparatus are provided for forming passive devices, such as a fuse (93) or resistor (95), in an active substrate region (103) by using heavy ion implantation (30) and annealing (40) to selectively form polycrystalline structures (42, 44) from a monocrystalline active layer (103), while retaining the single crystalline regions in the active layer (103) for use in forming active devices, such as NMOS and/or PMOS transistors (94). As disclosed, fuse structures (93) may be fabricated by forming silicide (90) in an upper region of the polycrystalline structure (42), while resistor structures (95) may be simultaneously formed from polycrystalline structure (44) which is selectively masked during silicide formation.Type: ApplicationFiled: October 1, 2008Publication date: April 1, 2010Inventors: Byoung W. Min, Satya N. Chakravarti