Abstract: A spiking neural network device comprises at least one NAND cell string including a first NAND cell string that includes a string select transistor and a plurality of nonvolatile memory cells between a bit line and a ground select line, a string control circuit configured to generate a string selection signal to turn on the string select transistor in response to an input spike, a word line decoder configured to generate a word line selection signal for selecting a word line of a plurality of word lines for each of the plurality of nonvolatile memory cells in response to the input spike, a plurality of sensing circuits connected to the bit line, respectively corresponding to the plurality of word lines, each sensing circuit configured to generate an output spike according to a current transmitted through the bit line when a corresponding word line is selected, a plurality of switch transistors, each configured to connect one of the plurality of sensing circuits to the bit line according to a switch selection

Abstract: A neuromorphic device includes a synaptic array, and a neuron circuit connected to the synaptic array, configured to accumulate an output current of the synaptic array, and configured to output a spike pulse when the accumulated current exceeds a threshold value, wherein a discharge switching element for discharging the current accumulated in the neuron circuit includes a synaptic element of the same type as an element included in the synaptic array.

Abstract: A neuromorphic device comprises a synaptic array including a plurality of word lines and bit lines and including a plurality of synaptic elements coupled to intersections of each of the word lines and the bit lines, a word line signal output unit that sequentially outputs a plurality of word line signals for activating the word lines, a signal pre-processing unit that preprocesses a spike signal to modulates the spike signal into an input signal, a weight summation unit including a plurality of weight summation circuits that respectively output a plurality of output signals obtained by applying respective weighted values stored in the synaptic array to a plurality of input signals input through the signal pre-processing unit, and a data output unit that transmits the output signals output by the weight summation unit respectively to a plurality of output neurons in response to the word line signal.

Abstract: Provided is an overpass-type semiconductor device and an overpass-type semiconductor device including a channel layer that overpasses a fin of a first gate. The overpass-type semiconductor device includes: a first gate including a fin having a preset height; a charge storage layer formed on the first gate and the fin; a channel layer formed on a part of the charge storage layer; a gate insulating layer formed on the channel layer; and a second gate formed on the gate insulating layer. The fin protrudes in a height direction from a center of the first gate, and the channel overpasses the fin.

Abstract: A hardware-based artificial neural network device includes a synaptic array including a plurality of capacitor-based synaptic cells, each having a variable capacitance according to a recorded weight, a word line selection unit including a plurality of switching elements respectively connected to word lines of the synaptic array, a bit line charging unit including a plurality of switching elements, each being connected to one end of each of bit lines of the synaptic array, and a bit line discharging unit including a plurality of switching elements, each being connected to the other end of each of the bit lines of the synaptic array.

Abstract: A spiking neural network providing device simulates a plurality of neuron layers and a plurality of synaptic layers, processes a spike signal, and applies a predetermined delay to timing when a bias is provided to the plurality of neuron layers.

Abstract: Provided is a neuron circuit that including: an input unit and an output unit and processes a signal transmitted through a synaptic array. The input unit receives weighted signals transmitted through the synaptic array and integrates the weighted signals as input signals, and discharge the integrated input signals until the amount of integrated input signal is less than or equal to a preset threshold. The output unit receives a signal output from the input unit, performs up-counting, and then generates an output signal while performing down-counting.

Abstract: Provided is a current mirror circuit and a neuromorphic device including the current mirror circuit and provides a current mirror circuit that causes an ideal current to flow through the current mirror circuit by using a compensation circuit, and a neuromorphic device including the current mirror circuit.

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure extending in a first direction. The semiconductor device includes an active pattern intersecting the gate structure and having a width in the first direction and a height in a second direction. The width is smaller than the height. Moreover, the semiconductor device includes a source/drain region electrically connected to the active pattern.

Abstract: Embodiments relate to a semiconductor device including a body made of a first conducting semiconductor material, a source and a drain made of a second conducting semiconductor material and formed on the body, a first gate formed on the body with a gate insulating layer interposed between the first gate and the body, a second gate formed opposite the first gate with respect to the body, and an insulating layer stack having a charge storage layer formed between the body and the second gate, and a method for controlling a synapse weight of a target semiconductor device within a neural network including semiconductor devices.

Abstract: A neural network using a cross-point array is provided along with a pattern readout method thereof. Resistive memory devices are stacked vertically to form the neural network as synaptic devices. The connection strength of the signal passing between two neurons is controlled by the positive and negative conductance of the resistive memory devices and it is possible to recognize and readout patterns by learning in the cross-point array.

Abstract: The present inventive concept provides a method for compensating a neuron threshold variation for firing in a neural network apparatus. The method compensates a threshold variation adjusting an effective threshold to a target threshold in each neuron. The effective threshold is for a next firing after the firing of each neuron.

Abstract: A resistive memory device and a method of operation of the resistive memory device are provided. The resistance memory device includes a resistance change layer that has a tunneling film and has many states. The conductance is changed symmetrically in a SET operation and a RESET operation. Thus, the resistive memory device can be used for efficient and accurate data storage as a RRAM in a high-capacity memory array, and as a synaptic device controlling the connection strength of a synapse in a neuromorphic system.

Abstract: Embodiments relate to an inference method and device using a spiking neural network including parameters determined using an analog-valued neural network (ANN). The spiking neural network used in the inference method and device includes an artificial neuron that may have a negative membrane potential or have a pre-charged membrane potential. Additionally, an inference operation by the inference method and device is performed after a predetermined time from an operating time point of the spiking neural network.

Abstract: The present invention relates to a resistance change memory, that is, a resistive memory device. By forming a bottom electrode from a doped semiconductor different material from a conventional one, it is possible to fabricate the memory device simultaneously with peripheral circuit elements. By having one or more electric field concentration regions in the bottom electrode, it is possible to reduce the power consumption reducing the voltage. The present invention can be also stacked vertically in any small and apply to the synaptic device array recently attracting the great interest as the next generation computing technology for realizing the neural imitation system.

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure extending in a first direction. The semiconductor device includes an active pattern intersecting the gate structure and having a width in the first direction and a height in a second direction. The width is smaller than the height. Moreover, the semiconductor device includes a source/drain region electrically connected to the active pattern.

Abstract: Semiconductor circuits are provided for emulating neuron firing process using a positive feedback transistor having first and second gate electrodes in the longitudinal direction of a channel region. The first gate electrode is connected to a gate electrode of a first p-channel MOSFET to be an input terminal and the second gate electrode is connected to a drain to be applied with a supply voltage. Thus electrons and holes can accumulate separately in a channel region (i.e., a body) under each of the gate electrodes by applying input signals to the input terminal and drastically reduce the wasted power consumption in the non-fired neurons because the current is turned on and off only at a moment that corresponds to a firing of the neuron. Thus, the semiconductor circuits can be driven by low power and have the same level of endurance as a general MOSFET.

Abstract: A resistive memory device and a method of operation of the resistive memory device are provided. The resistance memory device includes a resistance change layer that has a tunneling film and has many states. The conductance is changed symmetrically in a SET operation and a RESET operation. Thus, the resistive memory device can be used for efficient and accurate data storage as a RRAM in a high-capacity memory array, and as a synaptic device controlling the connection strength of a synapse in a neuromorphic system.

Abstract: A neural network using a cross-point array is provided along with a pattern readout method thereof. Resistive memory devices are stacked vertically to form the neural network as synaptic devices. The connection strength of the signal passing between two neurons is controlled by the positive and negative conductance of the resistive memory devices and it is possible to recognize and readout patterns by learning in the cross-point array.

Abstract: The present invention relates to a resistance change memory, that is, a resistive memory device. By forming a bottom electrode from a doped semiconductor different material from a conventional one, it is possible to fabricate the memory device simultaneously with peripheral circuit elements. By having one or more electric field concentration regions in the bottom electrode, it is possible to reduce the power consumption reducing the voltage. The present invention can be also stacked vertically in any small and apply to the synaptic device array recently attracting the great interest as the next generation computing technology for realizing the neural imitation system.