Patents by Inventor Byung Gook Park

Byung Gook Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190165268
    Abstract: A resistive memory device and a method of operation of the resistive memory device are provided. The resistance memory device includes a resistance change layer that has a tunneling film and has many states. The conductance is changed symmetrically in a SET operation and a RESET operation. Thus, the resistive memory device can be used for efficient and accurate data storage as a RRAM in a high-capacity memory array, and as a synaptic device controlling the connection strength of a synapse in a neuromorphic system.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 30, 2019
    Inventors: Byung-Gook Park, Min-Hwi Kim, Sungjun Kim
  • Publication number: 20190156208
    Abstract: A neural network using a cross-point array is provided along with a pattern readout method thereof. Resistive memory devices are stacked vertically to form the neural network as synaptic devices. The connection strength of the signal passing between two neurons is controlled by the positive and negative conductance of the resistive memory devices and it is possible to recognize and readout patterns by learning in the cross-point array.
    Type: Application
    Filed: November 21, 2018
    Publication date: May 23, 2019
    Inventors: Byung-Gook Park, Min-Hwi Kim, Sungjun Kim
  • Publication number: 20190148292
    Abstract: A semiconductor device includes a first conductive element, a first insulating layer and a second insulating layer sequentially disposed on the first conductive element, a conductive via passing through the first insulating layer and the second insulating layer. The conductive via is connected to the first conductive element. The semiconductor device includes a via extension portion disposed in the second insulating layer that extends along an upper surface of the first insulating layer from one side surface of the conductive via, and a second conductive element disposed on the second insulating layer that is connected to the via extension portion.
    Type: Application
    Filed: January 10, 2019
    Publication date: May 16, 2019
    Inventors: Yubo Qian, Byung Sung Kim, Hyeon Uk Kim, Young Gook Park, Chul Hong Park
  • Publication number: 20190131523
    Abstract: The present invention relates to a resistance change memory, that is, a resistive memory device. By forming a bottom electrode from a doped semiconductor different material from a conventional one, it is possible to fabricate the memory device simultaneously with peripheral circuit elements. By having one or more electric field concentration regions in the bottom electrode, it is possible to reduce the power consumption reducing the voltage. The present invention can be also stacked vertically in any small and apply to the synaptic device array recently attracting the great interest as the next generation computing technology for realizing the neural imitation system.
    Type: Application
    Filed: October 30, 2018
    Publication date: May 2, 2019
    Inventors: Byung-Gook Park, Sungjun Kim, Min-Hwi Kim, Tae-Hyeon Kim, Sang-Ho Lee
  • Publication number: 20180374938
    Abstract: Semiconductor circuits are provided for emulating neuron firing process using a positive feedback transistor having first and second gate electrodes in the longitudinal direction of a channel region. The first gate electrode is connected to a gate electrode of a first p-channel MOSFET to be an input terminal and the second gate electrode is connected to a drain to be applied with a supply voltage. Thus electrons and holes can accumulate separately in a channel region (i.e., a body) under each of the gate electrodes by applying input signals to the input terminal and drastically reduce the wasted power consumption in the non-fired neurons because the current is turned on and off only at a moment that corresponds to a firing of the neuron. Thus, the semiconductor circuits can be driven by low power and have the same level of endurance as a general MOSFET.
    Type: Application
    Filed: June 13, 2018
    Publication date: December 27, 2018
    Inventors: Byung-Gook Park, Min-Woo Kwon, Sungmin Hwang, Myung-Hyun Baek, Tae-Jin Jang
  • Publication number: 20180336451
    Abstract: An integrated circuit emulating a neural system and a fabricating method thereof are provided. A synapse device array that imitates a brain neural system (i.e., a central nervous system) requiring high integration on the same substrate is formed by stacking one or more layers on a lower portion, and a neuron circuit of a peripheral nervous system having sensory and motor neurons connected to the brain neural system is formed on an upper portion.
    Type: Application
    Filed: February 13, 2018
    Publication date: November 22, 2018
    Inventors: Byung-Gook Park, Seongjae Cho
  • Patent number: 10074435
    Abstract: A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers; verifying whether threshold voltages of a plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors; programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines; and program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selectio
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: September 11, 2018
    Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Byung Gook Park, Dae Woong Kwon, Do Bin Kim, Sang Ho Lee
  • Patent number: 10050195
    Abstract: A resistive random access memory device having a nano-scale tip and a nanowire is provided. A memory array using the same also is provided and fabrication method thereof. A technique is provided for forming a bottom electrode having an upwardly protruding tapered tip structure through etching a semiconductor substrate and a top electrode being formed of a nanowire and a technique forming a resistive random access memory device at a location intersected with each other in order that an area of each memory cell is minimized and that an electric field is focused on the tip of the bottom electrode across the top electrode.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: August 14, 2018
    Assignees: Seoul National University R&DB FOUNDATION, INCHEON UNIVERSITY INDUSTRY ACADEMIC COOPERATION FOUNDATION
    Inventors: Byung-Gook Park, Sung Hun Jin, Sunghun Jung, Minhwi Kim
  • Publication number: 20180197615
    Abstract: A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers; verifying whether threshold voltages of a plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors; programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines; and program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selectio
    Type: Application
    Filed: March 8, 2018
    Publication date: July 12, 2018
    Inventors: Byung Gook PARK, Dae Woong KWON, Do Bin KIM, Sang Ho LEE
  • Publication number: 20180190903
    Abstract: A resistive random access memory device having a nano-scale tip and a nanowire is provided. A memory array using the same also is provided and fabrication method thereof. A technique is provided for forming a bottom electrode having an upwardly protruding tapered tip structure through etching a semiconductor substrate and a top electrode being formed of a nanowire and a technique forming a resistive random access memory device at a location intersected with each other in order that an area of each memory cell is minimized and that an electric field is focused on the tip of the bottom electrode across the top electrode.
    Type: Application
    Filed: February 20, 2018
    Publication date: July 5, 2018
    Inventors: Byung-Gook Park, Sung Hun Jin, Sunghun Jung, Minhwi Kim
  • Patent number: 10014219
    Abstract: A semiconductor device includes a structure on a substrate and a plurality of gate-all-around devices on the structure. The structure includes a plurality of sacrificial layers and a plurality of active layers alternately stacked on one another. The sacrificial layers have different widths and the active layers have different widths to form multiple stepped layers on the substrate. The gate-all-around devices are on respective ones the multiple stepped layers.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: July 3, 2018
    Assignees: Samsung Electronics Co., Ltd., Seoul National University R & DB Foundation
    Inventors: Min-Chul Sun, Byung-Gook Park
  • Patent number: 9947413
    Abstract: A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers; verifying whether threshold voltages of a plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors; programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines; and program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selectio
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: April 17, 2018
    Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Byung Gook Park, Dae Woong Kwon, Do Bin Kim, Sang Ho Lee
  • Patent number: 9846838
    Abstract: The present invention provides a semiconductor circuit for emulating neuron firing process having a floating body device instead of the conventional capacitor. By using a floating body to store excess holes generated by impact ionization, it is possible to emulate signal accumulation of a neuron, trigger firing when the storage is in excess of a predetermined threshold value, and return to an original state after the firing.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: December 19, 2017
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Byung-Gook Park, Min-Woo Kwon, Hyungjin Kim
  • Patent number: 9799706
    Abstract: A resistive random access memory device is provided with a tunneling insulator layer between a resistance change layer and a bottom electrode. Thus, it is possible: to raise the selection (on/off) ratio by the current of a direct tunneling induced by low voltage in the unselected cell and the current of an F-N tunneling induced by high voltage in the selected cell, to efficiently suppress the leakage current in the read operation, to make a low current operation less ?A level by controlling the thickness of the tunneling insulator layer, and to be simultaneously fabricated together with circuit devices by forming the bottom electrodes (word lines) with a semiconductor material.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: October 24, 2017
    Assignees: Seoul National University R&DB Foundation, Gachon University of Industry-Academic Cooperation Foundation
    Inventors: Byung-Gook Park, Seongjae Cho, Sungjun Kim
  • Patent number: 9768381
    Abstract: The present invention relates to a resistive random access memory device having a nano-scale tip, memory array using the same and fabrication method thereof. Especially, the present invention provides a technique forming a bottom electrode having an upwardly protruding tapered tip structure through etching a semiconductor substrate in order that an electric field is focused on the tip of the bottom electrode across a top electrode and that a region where conductive filaments are formed is maximally minimized or localized.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: September 19, 2017
    Assignee: Seoul National University R&DB Foundation
    Inventors: Byung-Gook Park, Seongjae Cho, Sunghun Jung
  • Patent number: 9754673
    Abstract: A method of controlling a 3D non-volatile memory device includes initially leveling threshold voltages of the string selection transistors disposed in one or more of the plurality of memory layers to have a predetermined target level; applying a first time varying erase voltage signal having a first time varying section to a first plurality of channel lines of a first memory layer selected among the plurality of memory layers comprising the initially leveled string selection transistors; and setting threshold voltages of the initially leveled string selection transistors in the first memory layer by controlling each of the plurality of string selection lines respectively coupled with the initially leveled string selection transistors during the first time varying section of the first time varying erase voltage signal.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: September 5, 2017
    Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Byung Gook Park, Dae Woong Kwon, Do Bin Kim, Sang Ho Lee
  • Patent number: 9685235
    Abstract: A 3D non-volatile memory device may include a dummy string selection line, string selection lines, wordlines, bitlines, a ground selection line, and memory layers. Each of the memory layers comprising channel lines respectively coupled to the bitlines via first ends and coupled to a common source line of the memory layer via second ends. The dummy string selection line, the string selection lines, the wordlines, and the ground selection line intersect with the channel lines, and each of the channel lines defines a memory string. Initializing the 3D non-volatile memory device may include programming string selection transistors coupled with the string selection lines to have one or more threshold values, and programming a dummy string selection transistor coupled with the dummy string selection line to have a predetermined threshold value, such that the dummy string selection transistor together with the string selection transistors function as string selection transistors.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: June 20, 2017
    Assignees: SK HYNIX INC., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Byung Gook Park, Dae Woong Kwon, Do Bin Kim, Sang Ho Lee
  • Publication number: 20170162442
    Abstract: A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.
    Type: Application
    Filed: February 24, 2017
    Publication date: June 8, 2017
    Inventors: Min-Chul SUN, Byung-Gook PARK
  • Publication number: 20170140829
    Abstract: A 3D non-volatile memory device may include a dummy string selection line, string selection lines, wordlines, bitlines, a ground selection line, and memory layers. Each of the memory layers comprising channel lines respectively coupled to the bitlines via first ends and coupled to a common source line of the memory layer via second ends. The dummy string selection line, the string selection lines, the wordlines, and the ground selection line intersect with the channel lines, and each of the channel lines defines a memory string. Initializing the 3D non-volatile memory device may include programming string selection transistors coupled with the string selection lines to have one or more threshold values, and programming a dummy string selection transistor coupled with the dummy string selection line to have a predetermined threshold value, such that the dummy string selection transistor together with the string selection transistors function as string selection transistors.
    Type: Application
    Filed: November 14, 2016
    Publication date: May 18, 2017
    Inventors: Byung Gook PARK, Dae Woong KWON, Do Bin KIM, Sang Ho LEE
  • Publication number: 20170133095
    Abstract: A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers; verifying whether threshold voltages of a plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors; programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines; and program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selectio
    Type: Application
    Filed: November 3, 2016
    Publication date: May 11, 2017
    Inventors: Byung Gook PARK, Dae Woong KWON, Do Bin KIM, Sang Ho LEE