Patents by Inventor Byung-hee Kim

Byung-hee Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8912533
    Abstract: An organic light emitting display device which includes a base member; an organic light emitting display unit disposed on the base member and configured to generate an image; a sealing layer configured to seal the organic light emitting display unit; a capping substrate disposed on the sealing layer and having a plurality of metal layers, one of the metal layers being in contact with the sealing layer and having at least one groove; and a moisture absorbent provided in the groove.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: December 16, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung Hyun Son, Hoon Kim, Seung Kyu Park, Kie Hyun Nam, Byung Hee Kim
  • Patent number: 8872354
    Abstract: A method of forming through silicon vias (TSVs) uses a low-k dielectric material as a via insulating layer to thereby improve step coverage and minimize resistive capacitive (RC) delay. To this end, the method includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han Kyu-hee, Sang-hoon Ahn, Jang-hee Lee, Jong-min Beak, Kyoung-hee Kim, Byung-lyul Park, Byung-hee Kim
  • Publication number: 20140264892
    Abstract: A semiconductor device includes a first main strap, a second main strap, a plurality of first sub straps, a plurality of second sub straps, and a plurality of dummy lines. The first main strap is extended in a first direction. The second main strap is extended in the first direction. A plurality of first sub straps is branched from the first main strap. The plurality of second sub straps is branched from the second main strap. The plurality of dummy lines is positioned between the first main strap and the second main strap. Each of the plurality of dummy lines is positioned between each of the plurality of first sub straps and each of the plurality of second sub straps. Each of the dummy lines is spaced apart from the first main strap, the second main strap, each of the first sub straps and each of the second sub straps.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Soo Kim, Byung-Hee Kim
  • Publication number: 20140273432
    Abstract: A semiconductor device is fabricated by forming a lower conductor in a first interlayer dielectric film. A second interlayer dielectric film is formed on the lower conductor and the first interlayer dielectric film. A first hard mask pattern is formed on the second interlayer dielectric film. The first mask pattern has a first opening extending in a first direction. A planarization layer is formed on the first hard mask pattern. A mask pattern is formed on the planarization layer. The mask pattern has a second opening extending in a second direction perpendicular to the first direction. The lower conductor is positioned under an region where the first opening and the second opening overlap. A via hole and a trench connected to the via hole is formed using the first hard mask pattern and the mask pattern. The via hole exposes an upper surface of the lower conductor.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: BYUNG-HEE KIM, Tae-Soo Kim, Seong-Ho Park, Young-Ju Park, Ju-Young Jung
  • Patent number: 8736018
    Abstract: A semiconductor device comprises a top surface having a first contact, a bottom surface having a second contact, a via hole penetrating a substrate, an insulation layer structure on a sidewall of the via hole, the insulation layer structure having an air gap therein, a through electrode having an upper surface and a lower surface on the insulation layer structure, the through electrode filling the via hole and the lower surface being the second contact, and a metal wiring electrically connected to the upper surface of the through electrode and electrically connected to the first contact.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: May 27, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Hee Kim, Gil-Heyun Choi, Kyu-Hee Han, Byung-Lyul Park, Byung-Hee Kim, Sang-Hoon Ahn, Kwang-Jin Moon
  • Patent number: 8531349
    Abstract: A dual display module having a first display panel and a second display panel, the dual display module including a bezel arranged between the first display panel and the second display panel, and having a penetration area between the first display panel and the second display panel; and a supporting member arranged between the bezel and the second display panel and supporting the second display panel, the supporting member having at least one protrusion unit that protrudes through the penetration area to face the first display panel.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: September 10, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yoon-Chan Oh, Chan-Kyoung Moon, Kyoung-Soo Lee, Min-Hyeng Lee, Seon-Hee Kim, Gun-Mo Kim, Choong-Ho Lee, Byung-Hee Kim, Kuen-Dong Ha
  • Publication number: 20130228936
    Abstract: A method of forming through silicon vias (TSVs) uses a low-k dielectric material as a via insulating layer to thereby improve step coverage and minimize resistive capacitive (RC) delay. To this end, the method includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.
    Type: Application
    Filed: March 26, 2013
    Publication date: September 5, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu-hee Han, Sang-hoon Ahn, Jang-hee Lee, Jong-min Beak, Kyoung-hee Kim, Byung-lyul Park, Byung-hee Kim
  • Patent number: 8524615
    Abstract: Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: September 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hoon Ahn, Byung-Hee Kim, Sang-Don Nam, Kyu-Hee Han, Gil-heyun Choi, Jang-Hee Lee, Jong-Min Baek, Kyoung-Hee Kim
  • Patent number: 8501606
    Abstract: A semiconductor memory wiring method includes: receiving a substrate having a cell array region and a peripheral circuit region; depositing a first insulating layer on the substrate; forming a first contact plug in the cell array region, the first contact plug having a first conductive material extending through the first insulating layer; forming a first elongated conductive line at substantially the same time as forming the first contact plug, the first elongated conductive line having the first conductive material directly covering and integrated with the first contact plug; forming a second contact plug in the peripheral circuit region at substantially the same time as forming the first contact plug, the second contact plug having the first conductive material extending through the first insulating layer; and forming a second elongated conductive line at substantially the same time as forming the second contact plug, the second elongated conductive line having the first conductive material directly coveri
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: August 6, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Ok Lee, Dae-Yong Kim, Gil-Heyun Choi, Byung-Hee Kim
  • Patent number: 8486783
    Abstract: A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: July 16, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woong-hee Sohn, Byung-hee Kim, Dae-yong Kim, Min-sang Song, Gil-heyun Choi, Kwang-jin Moon, Hyun-su Kim, Jang-hee Lee, Eun-ji Jung, Eun-ok Lee
  • Patent number: 8426308
    Abstract: A method of forming through silicon vias (TSVs) includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: April 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-hee Han, Sang-hoon Ahn, Jang-hee Lee, Jong-min Beak, Kyoung-hee Kim, Byung-Iyul Park, Byung-hee Kim
  • Publication number: 20130087770
    Abstract: An organic light emitting display device which includes a base member; an organic light emitting display unit disposed on the base member and configured to generate an image; a sealing layer configured to seal the organic light emitting display unit; a capping substrate disposed on the sealing layer and having a plurality of metal layers, one of the metal layers being in contact with the sealing layer and having at least one groove; and a moisture absorbent provided in the groove.
    Type: Application
    Filed: June 4, 2012
    Publication date: April 11, 2013
    Applicant: SAMSUNG MOBILE DISPLAY CO., LTD.
    Inventors: Jung Hyun Son, Hoon Kim, Seung Kyu Park, Kie Hyun Nam, Byung Hee Kim
  • Patent number: 8404576
    Abstract: A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion reduction layer pattern on the metal ohmic layer pattern an amorphous layer pattern on the diffusion reduction layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: March 26, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Ho Cha, Seong-Hwee Cheong, Gil-Heyun Choi, Byung-Hee Kim, Hee-Sook Park, Jong-Min Baek
  • Publication number: 20130026503
    Abstract: An organic light emitting diode (OLED) display includes a substrate, an OLED on the substrate, and an encapsulation layer on the substrate with the OLED therebetween. The encapsulation layer includes a plurality of metal layers. Two of the plurality of metal layers are directly attached to each other.
    Type: Application
    Filed: May 17, 2012
    Publication date: January 31, 2013
    Inventors: Jung-Hyun Son, Hoon Kim, Byung-Hee Kim
  • Patent number: 8344664
    Abstract: In a power saving LED (Light Emitting Diode) display board system, each pixel is formed by combining at least one red LED, at least one blue LED and at least one green LED. The power saving LED display board system includes a power converter; a red LED power supply; a green LED power supply; a blue LED power supply; and a DSP (Digital Signal Processor) for controlling the red LED power supply to convert an electric power supplied from the power converter into a red LED operation power, controlling the green LED power supply to convert the electric power supplied from the power converter into a green LED operation power and controlling the blue LED power supply to convert the electric power supplied from the power converter into a blue LED operation power.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: January 1, 2013
    Assignees: Daecheong Masters
    Inventors: Byung Hee Kim, Sung Sil Kim
  • Publication number: 20120178253
    Abstract: The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer.
    Type: Application
    Filed: September 23, 2011
    Publication date: July 12, 2012
    Inventors: Sang-Hoon Ahn, Kyu-Hee Han, Kyoung-Hee Kim, Gil-Heyun Choi, Byung-Hee Kim, Sang-Don Nam
  • Publication number: 20120153500
    Abstract: A semiconductor device comprises a top surface having a first contact, a bottom surface having a second contact, a via hole penetrating a substrate, an insulation layer structure on a sidewall of the via hole, the insulation layer structure having an air gap therein, a through electrode having an upper surface and a lower surface on the insulation layer structure, the through electrode filling the via hole and the lower surface being the second contact, and a metal wiring electrically connected to the upper surface of the through electrode and electrically connected to the first contact.
    Type: Application
    Filed: December 8, 2011
    Publication date: June 21, 2012
    Inventors: Kyoung-Hee KIM, Gil-Heyun CHOI, Kyu-Hee HAN, Byung-Lyul PARK, Byung-Hee KIM, Sang-Hoon AHN, Kwang-Jin MOON
  • Patent number: 8173506
    Abstract: A method of forming a buried gate electrode prevents voids from being formed in a silicide layer of the gate electrode. The method begins by forming a trench in a semiconductor substrate, forming a conformal gate oxide layer on the semiconductor in which the trench has been formed, forming a first gate electrode layer on the gate oxide layer, forming a silicon layer on the first gate electrode layer to fill the trench. Then, a portion of the first gate electrode layer is removed to form a recess which exposed a portion of a lateral surface of the silicon layer. A metal layer is then formed on the semiconductor substrate including on the silicon layer. Next, the semiconductor substrate is annealed while the lateral surface of the silicon layer is exposed to form a metal silicide layer on the silicon layer.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: May 8, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-ji Jung, Hyun-soo Kim, Byung-hee Kim, Dae-yong Kim, Woong-hee Sohn, Kwang-jin Moon, Jang-hee Lee, Min-sang Song, Eun-ok Lee
  • Publication number: 20120094437
    Abstract: A method of forming through silicon vias (TSVs) includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.
    Type: Application
    Filed: September 19, 2011
    Publication date: April 19, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu-hee Han, Sang-hoon Ahn, Jang-hee Lee, Jong-min Baek, Kyoung-hee Kim, Byung-lyul Park, Byung-hee Kim
  • Publication number: 20120083117
    Abstract: Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer.
    Type: Application
    Filed: September 21, 2011
    Publication date: April 5, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Hoon Ahn, Byung-Hee Kim, Sang-Don Nam, Kyu-Hee Han, Gil-Heyun Choi, Jang-Hee Lee, Jong-Min Baek, Kyoung-Hee Kim