Abstract: A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.

Abstract: A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.

Abstract: A latency circuit for use in a semiconductor memory device includes a latency control clock generator generating an m-divided division signal from an external clock and at least one latency control clock from the m-divided division signal, wherein m is a natural number greater than or equal to 2. The latency circuit also includes a latency signal generator generating a latency signal in response to the at least one latency control clock, a latency control signal and an internal read command signal, wherein the latency control signal is generated from a column address strobe (CAS) latency and the internal read command signal is generated in response to a received read command.

Abstract: A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.

Abstract: A latency circuit comprises a latency control block, an internal read command generator, and a latency signal generation unit. The latency control block generates a plurality of first control clocks by delaying a delay sync signal generated based on an external clock, and generates a second control clock having a margin with respect to a read command decoded based on the delay sync signal. The internal read command generator samples the second control clock using the decoded read command and generates an internal read command based on a sampled second control clock. The latency signal generation unit generates a latency signal based on a shifting operation performed on the internal read command using the plurality of first control clocks.

Abstract: In an example embodiment, the semiconductor device includes a clock signal generation circuit. The clock signal generation circuit is configured to generate at least one control clock signal in response to an external clock signal and a read command signal. The clock signal generation circuit includes a plurality of delay circuits, and the clock signal generation circuit is configured to selectively disable at least one of the plurality of delay circuits to reduce power consumption.

Abstract: A latency circuit for use in a semiconductor memory device includes a latency control clock generator generating an m-divided division signal from an external clock and at least one latency control clock from the m-divided division signal, wherein m is a natural number greater than or equal to 2. The latency circuit also includes a latency signal generator generating a latency signal in response to the at least one latency control clock, a latency control signal and an internal read command signal, wherein the latency control signal is generated from a column address strobe (CAS) latency and the internal read command signal is generated in response to a received read command.

Abstract: Embodiments of the invention provide a column address strobe (CAS) latency circuit that generates a stable latency signal in a high-speed semiconductor memory device, and a semiconductor memory device including the CAS latency circuit. The CAS latency circuit may include an internal read command signal generator and a latency clock generator coupled to a latency signal generator. In an embodiment of the invention, the latency signal generator outputs a stable latency signal by shifting an internal read signal output from the internal read command signal generator based on latency control clocks output from the latency clock generator.

Abstract: A repair circuit and related method of repair are disclosed. In the repair circuit, row repair or column repair control units are selectively actuated to perform respective repair functions within a semiconductor memory device in relation to a commonly provided defective address. Both post-package defects and/or before package defects may be repaired in response to the defective address.

Abstract: A time delay compensation circuit comprises delay cells having various unit time delays. A delay-locked loop, a type of the time delay compensation circuit, includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes a plurality of delay cells having various unit time delays. The number of delay cells is adjusted in response to a predetermined shift signal. The delay line receives the external clock signal and outputs an output clock signal, which is obtained by controlling the phase of the external clock signal. The filter unit generates the shift signal, which selects the number of delay cells in the delay line, in response to the error control signal.

Abstract: A delay-locked loop includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes delay cells having various unit time delays. The number of delay cells is adjusted in response to a shift signal. The delay line receives the external clock signal and outputs an output clock signal. The filter unit generates the shift signal in response to the error control signal. In the delay-locked loop, the front delay cells, which compensate for a delay of an external clock signal having a high frequency, have short unit time delays. The rear delay cells, which compensate for a delay of the external clock signal having a low frequency, have long unit time delays.

Abstract: Embodiments of the invention provide a column address strobe (CAS) latency circuit that generates a stable latency signal in a high-speed semiconductor memory device, and a semiconductor memory device including the CAS latency circuit. The CAS latency circuit may include an internal read command signal generator and a latency clock generator coupled to a latency signal generator. In an embodiment of the invention, the latency signal generator outputs a stable latency signal by shifting an internal read signal output from the internal read command signal generator based on latency control clocks output from the latency clock generator.

Abstract: A delay-locked loop (DLL) is disclosed with a phase detector configured to detect a phase difference between an external clock signal and an internal clock signal, a variable delay line configured to variably delay the external clock signal in relation to the phase difference to generate an intermediate clock signal, a selection unit configured to select between the intermediate clock signal and an inverted version of the intermediate clock signal in relation to an inversion control signal, and to generate an internal clock signal according to the selection, and an inversion determination unit configured to generate the inversion control signal in relation to transition of the external clock signal within a duty error margin.

Abstract: A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.

Abstract: A delay-locked loop (DLL) is disclosed with a phase detector configured to detect a phase difference between an external clock signal and an internal clock signal, a variable delay line configured to variably delay the external clock signal in relation to the phase difference to generate an intermediate clock signal, a selection unit configured to select between the intermediate clock signal and an inverted version of the intermediate clock signal in relation to an inversion control signal, and to generate an internal clock signal according to the selection, and an inversion determination unit configured to generate the inversion control signal in relation to transition of the external clock signal within a duty error margin.

Abstract: We describe and claim an internal signal replication device and method. A circuit comprising a selector to select one of a plurality of internally generated clock signals, and a compensation circuit to replicate the selected clock signal from a reference clock signal.

Abstract: A repair circuit and a method of repairing defects in a semiconductor memory device are disclosed. The repair circuit of a semiconductor memory device includes an address generating unit, an address electrical fuse (e-fuse) box unit, a row/column selecting e-fuse unit, a row repair control unit, and a column repair control unit. The address generating unit generates a row address or a column address in response to a control signal, the address e-fuse box unit stores a defective address after packaging, and the row/column selecting e-fuse unit generates a select signal for determining whether the defective address corresponds to a row defect or a column defect. The row repair control unit compares the defective address after packaging with the row address in response to a first state of the select signal, and the column repair control unit compares the defective address after packaging with the column address in response to a second state of the select signal.

Abstract: A Delayed Lock Loop (DLL) circuit includes an inversion control circuit. The inversion control circuit includes an inversion decision circuit to determine the inversion of reproduction clock signal by comparing phases of an external clock signal and a reproduction clock signal, and to produce an inversion decision signal including a duty error margin for the reproduction clock signal. The inversion control circuit also includes an output latch to latch the inversion decision signal in synchronization with a start signal to produce an inversion control signal.

Abstract: Decoupling capacitance of at least one shared capacitor is distributed among a plurality of voltage sources for enhanced performance with minimized area of a semiconductor device. The high nodes and the low nodes of such voltage sources each comprise at least two distinct nodes for lower noise at the voltage sources. The present invention is applied to particular advantage for coupling a variable number of shared capacitors to a data charge voltage source depending on a bit organization of the semiconductor device.

Abstract: A circuit for controlling timing skew in a semiconductor memory device includes a skew control circuit that is configured generate separate skew control signals for each respective one of a plurality of memory banks included in the semiconductor memory device. Related methods are also disclosed.