Abstract: A method of forming a silicon nitride layer in a semiconductor device manufacturing process. The silicon nitride layer (SixNyHz) is formed by PE-CVD technique at low temperature to have at most 0.35 hydrogen composition. The resulting silicon nitride layer has substantially no Si—H bonding as compared with a silicon nitride layer formed at high temperature, thereby reducing thermal stress variation during annealing. The resulting silicon nitride layer exhibits reduced thermal stress variation before and after deposition, preventing a popping phenomenon and reducing the stress applied to the underlying layer.

Abstract: A dielectric layer is formed by depositing a first dielectric layer above a semiconductor substrate including recessed regions, etching the first dielectric layer to remove any voids and to lower the aspect ratio of the recessed regions, and depositing a second dielectric layer on the first dielectric layer in the recessed regions. The method is particularly useful when the aspect ratios are high for recessed regions formed between patterns.

Abstract: A dielectric layer is formed by depositing a first dielectric layer above a semiconductor substrate including recessed regions, etching the first dielectric layer to remove any voids and to lower the aspect ratio of the recessed regions, and depositing a second dielectric layer on the first dielectric layer in the recessed regions. The method is particularly useful when the aspect ratios are high for recessed regions formed between patterns.

Abstract: A method for forming a microelectronic device includes the steps of forming a spin-on-glass layer on a microelectronic substrate, and forming a capping layer on the spin-on-glass layer opposite the substrate. A masking layer is formed on the capping layer opposite the substrate wherein the masking layer exposes portions of the capping layer and the spin-on-glass layer. The exposed portions of said capping layer and the spin-on-glass layer are etched using the masking layer as an etch mask to thereby form a contact hole through the capping layer and the spin-on-glass layer wherein protruding edge portions of the capping layer extend beyond the spin-on-glass layer adjacent the contact hole. The mask layer is removed, and the protruding edge portions of the capping layer are removed from adjacent the contact hole.

Abstract: A method for stabilizing an interlevel dielectric layer formed by a chemical vapor deposition (CVD) process, using electron beams. A CVD oxide layer is formed on a semiconductor substrate. The CVD oxide layer is radiated with electron beams at a temperature of between approximately room temperature and approximately 500.degree. C. for a predetermined time, using an electron beam radiator, to densify the layer.

Abstract: An insulating layer may be fabricated on a microelectronic substrate by spinning a layer of spin-on-glass (SOG) on a microelectronic substrate and curing the SOG layer by irradiating the SOG layer with an electronic beam. Irradiating may take place simultaneously with heating the substrate to a temperature below about 500.degree. C. An underlying and/or overlying capping layer may also be provided. Alternatively, rather than irradiating the SOG layer, an overlying capping layer may be irradiated.

Abstract: A method for forming an insulating layer for a microelectronic device includes the steps of forming a conductive pattern on a surface of a microelectronic substrate, and forming a spin-on-glass layer on the surface of the microelectronic substrate covering the conductive pattern. The spin-on-glass layer is baked at a temperature in the range of 400.degree. C. to 750.degree. C., and a moisture blocking layer is formed on the baked spin-on-glass layer. By reducing moisture absorbed from the air into the spin-on-glass layer, a relatively low etch rate and a relatively low dielectric constant can be maintained for the spin-on-glass layer. Related structures are also discussed.

Abstract: A method for forming a conductive line uses a fluorine doped oxide layer as an insulating layer between conductive lines. The method comprises the steps of: (a) forming a fluorine doped oxide layer on a semiconductor substrate on which a lower structure is formed; (b) etching the oxide layer of the region where a conductive line is to be formed, thereby forming a trench; (c) forming an insulating layer on the overall surface of the resultant substrate; depositing conductive material on the resultant substrate; and (e) etching back the conductive material so that the conductive material is left on the trench only, thereby forming a conductive line. In this method, the conductive line is formed of aluminum-containing material and the insulating layer is formed of silicon dioxide. In the present invention, the insulating layer is interposed between the fluorine doped oxide layer and the aluminum-containing conductive line and thus the conductive line is free from corrosion.