Patents by Inventor Byung-Se So

Byung-Se So has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10313217
    Abstract: A system on chip structured in a second network device is provided. The system on chip includes: a first resource which is structured as at least one of hardware and software; a resource management module; and a processor configured to control or execute the resource management module to monitor a state of the first resource, and manage a sharing condition of the first resource to be shared by a first network device and the second network device and shared information of at least one second resource which is hardware and/or software, currently shared by the second network device and a third network device.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin Min Kim, Bo Gyeong Kang, Myung Koo Kang, Dae Hwan Kim, Byung Se So
  • Publication number: 20160337322
    Abstract: A method of operating a hub which manages user data communicated between a server and a plurality of internet of things (IoT) devices includes storing a user data management rule set by a user, processing sensitive data among user data transmitted from one of the IoT devices according to the user data management rule to generate processed data, and transmitting the processed data to the server.
    Type: Application
    Filed: May 11, 2016
    Publication date: November 17, 2016
    Inventors: BO GYEONG KANG, MYUNG KOO KANG, BYUNG SE SO, DAE HWAN KIM, JAE WOO JUNG, HYUN WOO CHUNG, SANG HWA JIN
  • Publication number: 20160323283
    Abstract: A method of operating a hub includes the hub receiving a pairing request from an Internet of Things (IoT) device, the hub performing pairing with the IoT device using one authentication technique from among a plurality of predetermined pairing authentication techniques, and the hub assigning an access right to a resource to the IoT device. The access right is determined according to the one authentication technique.
    Type: Application
    Filed: April 29, 2016
    Publication date: November 3, 2016
    Inventors: BO GYEONG KANG, MYUNG KOO KANG, BYUNG SE SO, SANG HWA JIN
  • Publication number: 20160269259
    Abstract: A system on chip structured in a second network device is provided. The system on chip includes: a first resource which is structured as at least one of hardware and software; a resource management module; and a processor configured to control or execute the resource management module to monitor a state of the first resource, and manage a sharing condition of the first resource to be shared by a first network device and the second network device and shared information of at least one second resource which is hardware and/or software, currently shared by the second network device and a third network device.
    Type: Application
    Filed: March 10, 2016
    Publication date: September 15, 2016
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin Min KIM, Bo Gyeong KANG, Myung Koo KANG, Dae Hwan KIM, Byung Se SO
  • Patent number: 8051343
    Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: November 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
  • Publication number: 20110113296
    Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.
    Type: Application
    Filed: October 22, 2010
    Publication date: May 12, 2011
    Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
  • Patent number: 7930465
    Abstract: A semiconductor memory device capable of determining an operation mode by using states of data pins, and an operation mode determining method for the same are disclosed. The semiconductor memory device includes at least one MRS input pad, at least one data input pad, and an operation mode determining circuit. The operation mode determining circuit generates an operation mode determining signal, when an MRS command input through the MRS input pad corresponds to a predetermined MRS command and data signals input through the data input pad or pads include a predetermined combination. Accordingly, the efficiency in the manufacturing and producing processes may be improved by determining the operation mode of the semiconductor memory device in a module assembly process.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: April 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Il Kim, Young-Man Ahn, Byung-Se So, Seung-Jin Seo
  • Patent number: 7868438
    Abstract: Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: January 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Se So, Dong-Ho Lee, Hyun-Soon Jang
  • Patent number: 7847383
    Abstract: A multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The input/output pad of the first semiconductor chip directly receives an input/output signal via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: December 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Se So, Dong-Ho Lee
  • Patent number: 7849373
    Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: December 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
  • Patent number: 7818488
    Abstract: Pairs of registers with reduced pins are disposed to overlap on front and back surfaces of a memory module. An input signal INS is transferred through the registers in series in a daisy chain fashion to avoid divergence of the input signal INS for preserved signal integrity. Each register buffers the input signal INS to memory banks disposed closely to sides of the register for reduced wiring area.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: October 19, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-Soo Park, Jeong-Hyeon Cho, Byung-Se So, Jung-Joon Lee, Young Yun, Kwang-Seop Kim
  • Patent number: 7656181
    Abstract: A test apparatus capable of detecting input/output (I/O) circuit characteristics of a semiconductor device by analyzing an eye mask generated in the test apparatus and the waveform of a test signal output from the I/O circuit of the semiconductor device. The test apparatus includes an eye mask generator that generates an eye mask in synchronization with one or more clock signals of opposite phase to each other, an error detector that receives the eye mask from the eye mask generator and compares the test signal with the eye mask to determine whether an error occurs in the semiconductor device, and an error signal output unit that receives an error detection signal from the error detector and generates an error signal in response to the error detection signal.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: February 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Seop Kim, Jun-Young Park, Sung-Je Hong, Sung-Bum Cho, Byung-Se So, Hyun-Chul Kang
  • Patent number: 7615869
    Abstract: Embodiments are described in which a stacked arrangement of integrated circuit packages comprises a dummy substrate comprising an embedded discrete or distributed capacitor connected to first and/or second power voltages, or an embedded termination register connected to one or more clock, control, address, and/or data signals(s).
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: November 10, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Woo Koo, Byung-Se So, Young-Jun Park
  • Patent number: 7606110
    Abstract: A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock and generating one or more internal periodic clocks and a plurality of memory units, receiving one of the internal periodic clocks or a non-periodic clock from an external source.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: October 20, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: You-Keun Han, Hui-Chong Shin, Seung-Jin Seo, Byung-Se So, Young-Man Ahn, Seung-Man Shin, Jung-Kuk Lee, Ho-Suk Lee
  • Patent number: 7566958
    Abstract: Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: July 28, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Se So, Dong-Ho Lee, Hyun-Soon Jang
  • Patent number: 7539910
    Abstract: A memory module test system including at least one memory module. The at least one memory module includes a first hub and a plurality of semiconductor memory devices. The system includes a tester for testing the at least one memory module. A second hub is located between the first hub and the tester. The second hub is for converting a memory command and memory data output from the tester into packet data and transmits the packet data to the first hub. The second hub converts the packet data output from the first hub into memory data and transmits the memory data to the tester.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: May 26, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Man Ahn, Byung-Se So, Seung-Jin Seo, Seung-Man Shin
  • Publication number: 20090079496
    Abstract: Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed.
    Type: Application
    Filed: September 26, 2008
    Publication date: March 26, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-Se SO, Dong-Ho LEE, Hyun-Soon JANG
  • Patent number: 7505521
    Abstract: A data transmission system and method characterized by the use of multiple differential output amplifiers to transmits differential data signals that vary in accordance with control signals derived from a reference data output strobe signal, and multiple differential amplifiers to receive the differential data signals and detect such variations to generate a data input strobe signal corresponding to the data output strobe signal.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: March 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Hyeon Cho, Jae-Jun Lee, Jong-Hoon Kim, Byung-Se So
  • Publication number: 20090044062
    Abstract: A method of testing a memory module comprising converting a hub of the memory module into a transparent mode, providing first data corresponding to a first address to the hub of the memory module, providing the first data of the hub of the memory module to a first address of a memory, providing first expected data to the hub of the memory module, outputting second data stored at the first address of the memory to the hub of the memory module, and comparing the second data with the first expected data.
    Type: Application
    Filed: September 30, 2008
    Publication date: February 12, 2009
    Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
  • Patent number: 7447954
    Abstract: A method of testing a memory module comprising converting a hub of the memory module into a transparent mode, providing first data corresponding to a first address to the hub of the memory module, providing the first data of the hub of the memory module to a first address of a memory, providing first expected data to the hub of the memory module, outputting second data stored at the first address of the memory to the hub of the memory module, and comparing the second data with the first expected data.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: November 4, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han