Abstract: A method of testing an integrated circuit includes providing a bank access sequence received to a register in the integrated circuit, generating a test pattern sequence based on the bank access sequence, and performing a Built-In Self Test (BIST) operation on the integrated circuit based on the generated test pattern sequence.

Abstract: A memory module includes a first set of at least one first type of memory device and a second set of at least one second type of memory device having a higher capacity than the first type. In addition, an additional capacity portion of the first and second sets stores information for an additional function of the memory module, and a remaining capacity portion of the first and second sets forms a rank of the memory module. The memory module avoids an asymmetric topology of signal lines and yet provides additional memory capacity.

Abstract: Embodiments of the invention include a stacked board-on-chip (BOC) package having a mirroring structure and a dual inline memory module (DIMM) on which the stacked BOC package is mounted. A bottom surface of a first semiconductor chip faces a bottom surface of a second semiconductor chip. An interposer electrically connects first and second packages, respectively comprising the first and second semiconductor chips, to each other. The DIMM is obtained by electrically connecting BOC packages to each other on upper and lower substrates of a printed circuit board. Since a height of the stacked BOC packages is greater than a height of a conventional stacked BOC package, the DIMM has a minimum stub length and an optimal topology. Hence, the DIMM can have a signal with excellent fidelity by reducing a load upon a signal line, and installation or wiring of components within the DIMM 300 requires less effort.

Abstract: A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock and generating one or more internal periodic clocks and a plurality of memory units, receiving one of the internal periodic clocks or a non-periodic clock from an external source.

Abstract: A memory module is capable of constituting short loop-through form memory bus systems in which the length of the entire channel can be reduced. As a result, the systems are suitable for a high-speed operation, and costs for fabricating systems such as a board and a module connector can be reduced. The memory module includes a plurality of tabs located in one side of the front and in one side on the rear of the memory module, for being interconnected by a connector on a system board, a plurality of vias for connecting two different signal layers of the memory module, and a plurality of data buses extended from the tabs on the front of the memory module to the tabs on the rear of the memory module through each of the vias. At least one memory device is connected to each of the data buses. Preferably, each of the data buses is formed to be perpendicular to one side of the memory module on which the tabs are formed.

Abstract: A method of testing a memory module comprising converting a hub of the memory module into a transparent mode, providing first data corresponding to a first address to the hub of the memory module, providing the first data of the hub of the memory module to a first address of a memory, providing first expected data to the hub of the memory module, outputting second data stored at the first address of the memory to the hub of the memory module, and comparing the second data with the first expected data.

Abstract: For ODT (on-die termination) control within a memory module system, just one pin from the memory controller is used for sending command signals indicating an activated one of the memory devices. The activated memory device includes components that are turned on for generating the ODT control signal for controlling an ODT circuit of inactivated memory device(s). The components for generating an ODT control signal within the inactivated memory devices are turned off for minimized power consumption.

Abstract: Memory modules and methods of testing memory modules are provided that include at least one memory device responsive to a memory clock signal having a memory clock frequency and a data buffer. The data buffer is responsive to a buffer clock signal having a first buffer clock frequency that is different from the memory clock frequency during a normal mode of operation and having a second buffer clock frequency that is equal to the memory clock frequency during a test mode of operation.

Abstract: The present invention discloses a memory module and a method of arranging a signal line of the same.

Abstract: Embodiments of the present invention may include an integrated circuit module structure for a high-density mounting. An embodiment may include a wiring board, having a mounting space with a mounting length determined in a first direction and a mounting width determined in a second direction, on at least one surface thereof, and a plurality of integrated circuit packages having a package mounting combination length longer than the mounting length of the wiring board. An embodiment may also have some packages among the plurality of integrated circuit packages mounted directly on the mounting space, while other packages are mounted indirectly on the mounting space. The present embodiment may have packages that are overlapped horizontally and vertically distant from one another. Embodiments allow a plurality of chips or packages to be mounted in a limited area without changing a form factor of integrated circuit module even when integrated circuit chip or package size increases.

Abstract: Pairs of registers with reduced pins are disposed to overlap on front and back surfaces of a memory module. An input signal INS is transferred through the registers in series in a daisy chain fashion to avoid divergence of the input signal INS for preserved signal integrity. Each register buffers the input signal INS to memory banks disposed closely to sides of the register for reduced wiring area.

Abstract: A data transmission system and method characterized by the use of multiple differential output amplifiers to transmits differential data signals that vary in accordance with control signals derived from a reference data output strobe signal, and multiple differential amplifiers to receive the differential data signals and detect such variations to generate a data input strobe signal corresponding to the data output strobe signal.

Abstract: A system board includes a control unit; connectors arranged in series in one direction and accepting a connecting means for inputting and outputting data; and signal lines connecting the control unit to the connectors and including at least one branch point, wherein sub signal lines branched off at the same branch point are equal in length and/or loads of path from the branch point to the connecting means.

Abstract: In the memory module, a buffer is disposed on one of at least two circuit boards in the memory module. The buffer is for buffering signals for memory chips on at least two circuit boards in the memory module.

Abstract: A memory module test system including at least one memory module. The at least one memory module includes a first hub and a plurality of semiconductor memory devices. The system includes a tester for testing the at least one memory module. A second hub is located between the first hub and the tester. The second hub is for converting a memory command and memory data output from the tester into packet data and transmits the packet data to the first hub. The second hub converts the packet data output from the first hub into memory data and transmits the memory data to the tester.

Abstract: The present invention provides a memory module, comprising: a plurality of semiconductor memory devices for writing and reading m-bit parallel data; and a buffer for converting n-bit serial data into the m-bit parallel data to output to the plurality of semiconductor memory devices, converting the m-bit parallel data into the n-bit serial data to output to a first external portion during a normal operation, buffering 2n-bit parallel data to output to the plurality of semiconductor memory devices, and buffering the m-bit parallel data to output to a second external portion during a test operation.

Abstract: A memory system includes a memory controller, a memory bus connected to the memory controller, and a plurality of memory modules connected along the memory bus, where each of the memory modules includes a plurality of memory devices. The system also includes a dummy stub or a dummy module connected to the memory bus between the memory controller and the memory module closest to the memory controller among the plurality of memory modules. The dummy stub or dummy module improves a signal integrity of at least the memory module closest to the memory controller.

Abstract: A buffered memory module includes a buffer circuit mounted and a plurality of memory devices mounted on the first surface of the board, the memory devices being electrically connected to the buffer circuit. The memory module also includes a plurality of test pads located on a second surface of the board and electrically connected to the buffer circuit.

Abstract: A ball grid array (BGA) package test module includes BGA packages, a module board, and test architecture for use in testing the BGA packages while they are mounted to the module board. The test architecture of the BGA package test module includes package test signal lines connected to solder balls of the BGA packages as extending along a bottom surface of the BGA packages, board test signal lines extending along the module board, and electrical junctions that interconnect the package and board test signal lines. Signals from the BGA packages can be picked up by the probe of a testing apparatus via the board test signal lines. The present invention is advantageous in that it minimizes the effect of stubbing by the test signal lines when the memory module is operating.

Abstract: A ball grid array (BGA) package test module includes BGA packages, a module board, and test architecture for use in testing the BGA packages while they are mounted to the module board. The test architecture of the BGA package test module includes package test signal lines connected to solder balls of the BGA packages as extending along a bottom surface of the BGA packages, board test signal lines extending along the module board, and electrical junctions that interconnect the package and board test signal lines. Signals from the BGA packages can be picked up by the probe of a testing apparatus via the board test signal lines. The present invention is advantageous in that it minimizes the effect of stubbing by the test signal lines when the memory module is operating.