Abstract: A memory module is capable of constituting short loop-through form memory bus systems in which the length of the entire channel can be reduced. As a result, the systems are suitable for a high-speed operation, and costs for fabricating systems such as a board and a module connector can be reduced. The memory module includes a plurality of tabs located in one side of the front and in one side on the rear of the memory module, for being interconnected by a connector on a system board, a plurality of vias for connecting two different signal layers of the memory module, and a plurality of data buses extended from the tabs on the front of the memory module to the tabs on the rear of the memory module through each of the vias. At least one memory device is connected to each of the data buses. Preferably, each of the data buses is formed to be perpendicular to one side of the memory module on which the tabs are formed.

Abstract: A memory system includes a chipset mounted on a circuit board, and first and second memory module connectors mounted respectively on the circuit board. The first and second memory modules are inserted into the first and second memory module connectors, respectively. The memory system further includes a bus connected to the chipset and the first and second memory module connectors so to create a branch point. Each of the first and second memory modules includes at least one memory device connected to the bus via a stub line and a stub resistor. Impedance of the bus is less than that of the stub line.

Abstract: A chip scale package has first and second sets of external signal terminals arranged in rows and columns at respective sides of the bottom surface of the package The spacing between the rows of the first set of signal terminals is greater than the spacing between the rows of the second set of signal terminals. The chip scale packages are mounted to and integrated by a printed circuit board having corresponding lands in each of a plurality of chip scale package regions. Thus, the spacing between adjacent rows of a first set of lands is greater than the spacing between adjacent rows of a second set of lands. The rows of the first lands are spaced wider apart so that a plurality of first signal lines can extend contiguously between each adjacent pair of rows of first lands, in each of the chip scale package regions. A method of designing the printed circuit board lays out the lands of the PCB in rows and columns, sets the spacing thereof, and traces out the signal lines.

Abstract: A transmission circuit that conducts signals between integrated circuit devices includes a first driver circuit that generates a first transmit signal in response to first and second input signals, the first transmit signal being transmitted from the integrated circuit device. A first conductive line is electrically coupled to the first driver circuit and conducts the first transmit signal. A second driver circuit generates a second transmit signal in response to the first transmit signal and a third input signal, the second transmit signal being transmitted from the integrated circuit device. A second conductive line is electrically coupled to the second driver circuit and conducts the second transmit data signal. Related methods are also disclosed.

Abstract: A memory module is capable of constituting short loop-through form memory bus systems in which the length of the entire channel can be reduced. As a result, the systems are suitable for a high-speed operation, and costs for fabricating systems such as a board and a module connector can be reduced. The memory module includes a plurality of tabs located in one side of the front and in one side on the rear of the memory module, for being interconnected by a connector on a system board, a plurality of vias for connecting two different signal layers of the memory module, and a plurality of data buses extended from the tabs on the front of the memory module to the tabs on the rear of the memory module through each of the vias. At least one memory device is connected to each of the data buses. Preferably, each of the data buses is formed to be perpendicular to one side of the memory module on which the tabs are formed.

Abstract: A multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal from a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other.

Abstract: An integrated circuit device includes a delay circuit that is configured to delay a clock signal and is further configured to generate an output data signal in response to the delayed clock signal and an input data signal. Multiple devices are configured to respectively receive the output data signal in response to the clock signal.

Abstract: A transmission circuit that conducts signals between integrated circuit devices includes a first driver circuit that generates a first transmit signal in response to first and second input signals, the first transmit signal being transmitted from the integrated circuit device. A first conductive line is electrically coupled to the first driver circuit and conducts the first transmit signal. A second driver circuit generates a second transmit signal in response to the first transmit signal and a third input signal, the second transmit signal being transmitted from the integrated circuit device. A second conductive line is electrically coupled to the second driver circuit and conducts the second transmit data signal. Related methods are also disclosed.

Abstract: The semiconductor memory system includes a memory controller, N system data buses, and first through P-th memory module groups. The N system data buses are connected to the memory controller and respectively have a width of M/N bits. The first through P-th memory module groups are connected to the N system data buses and respectively have N memory modules. In each of the first through P-th memory module groups, a different one of the N system data buses is connected to each of the N memory modules, and each of the N system data buses has a data bus width of M/N bits. The first through P-th memory module groups are operated in response to first through P-th corresponding chip select signals. M is the bit-width of an entire system data bus of the semiconductor memory system. The N system data buses are wired such that data transmission times are the same from each N memory modules that operate in response to the same chip select signal to the memory controller.

Abstract: A memory system system includes a single in-line memory module (SIMM) which contains a memory device and a signal transmission line connected between the memory device and a connection terminal, and a dual in-line memory module (DIMM) which contains two memory devices and a signal transmission line connected between the two memory devices and a connection terminal. A length of the signal tranmission line of the SIMM is longer than a length of the signal transmission line of the DIMM. The load of the memory device of the SIMM is less than the load of memory devices of the DIMM, and the longer length of the signal tranmission line of the SIMM increases a signal delay time of the SIMM to compensate for the different loads of the SIMM and DIMM memory devices. The longer length of the signal tranmission line of the SIMM may further compensate for a signal transmission line connected between the first and second sockets which receive the SIMM and DIMM, respectively.

Abstract: A memory module and a method of packaging memory devices are provided. The method prepares semiconductor packages of the memory devices, each of which has external pins that include data pins and command signal pins, and mounts the packages on a printed circuit board, on which a first bus, a second bus, and a third bus are formed. The data pins of odd-numbered packages and even-numbered packages connect to the first bus and the second bus, respectively. The control signal pins connect to the third bus. Each package can optionally include dummy pins, where the dummy pins of the even-numbered packages and the odd-numbered packages respectively connect to the first and second buses so that each of the first, second and third buses connects to the same number of external pins. The pin assignment of the even-numbered packages can be different from the pin assignment of the odd-numbered packages to facilitate connections of the buses.

Abstract: A memory system includes a chipset mounted on a circuit board, and first and second memory module connectors mounted respectively on the circuit board. The first and second memory modules are inserted into the first and second memory module connectors, respectively. The memory system further includes a bus connected to the chipset and the first and second memory module connectors so to create a branch point. Each of the first and second memory modules includes at least one memory device connected to the bus via a stub line and a stub resistor. Impedance of the bus is less than that of the stub line.

Abstract: Semiconductor device testers are provided which measure skew between two or more output pins of a semiconductor device independent of a strobe timing input. More particularly, a skew signal is generated by a comparator circuit that changes state when the respective outputs transition state, for example, from matching to differing states. In a two output pin embodiment, for instance, when one of the output pin changes state before the other and both initially are in the same state, a flip flop is set at the time when the data on the output pins first differs, i.e. when the first output pin transitions to a new state. The flip flop is then reset when the second output pin subsequently transitions to the new state and again matches the first output pin. The resulting duration of the output of the flip flop thereby corresponds to the time of skew of the output pins regardless of the initial state of the pins.

Abstract: A system board includes a control unit; connectors arranged in series in one direction and accepting a connecting means for inputting and outputting data; and signal lines connecting the control unit to the connectors and including at least one branch point, wherein sub signal lines branched off at the same branch point are equal in length and/or loads of path from the branch point to the connecting means.

Abstract: A memory module for use with a computer system board includes at least one memory chip connected to a bus line conductor and a terminating resistor connected to the bus line conductor. The memory module further includes a connector configured to connect the bus line conductor to bus line of the computer system board. A computer system board includes a bus line including first branch configured to connect to a first memory module and a second branch configured to connect to a second memory module. The computer system board further includes a memory controller coupled to the first and second branches of the bus line at a single pin thereof. In other embodiments, a computer system board includes a bus line having first and second branches. A first switch is operative to selectively couple a first plurality of memory modules to a first branch of a bus line of the system board. A second switch is operative to selectively couple a second plurality of memory modules to the second branch of the bus line.

Abstract: A memory system having a stub-bus configuration transmits a free-running clock through the same path as data signals. A single clock domain is employed for both read and write operations. For both operations, the read or write clock signal is routed through the same transmission path as the data, thereby increasing system transfer rates by maximizing the window of data validity. In this manner, data bus utilization is increased due to the elimination of a need for a preamble interval for the strobe signal, and pin count on the memory module connectors is therefore reduced.

Abstract: Memory modules and methods of testing memory modules are provided that include at least one memory device responsive to a memory clock signal having a memory clock frequency and a data buffer. The data buffer is responsive to a buffer clock signal having a first buffer clock frequency that is different from the memory clock frequency during a normal mode of operation and having a second buffer clock frequency that is equal to the memory clock frequency during a test mode of operation.

Abstract: An integrated circuit device includes a delay circuit that is configured to delay a clock signal and is further configured to generate an output data signal in response to the delayed clock signal and an input data signal. Multiple devices are configured to respectively receive the output data signal in response to the clock signal.

Abstract: A memory system, which can improve the operation speed of a data bus and is suitable for widening bandwidth by extending the width of the data bus, and memory modules used for the memory system are provided. In the memory system, data buses of a first channel and data buses of a second channel are extended from a memory controller and are arranged on the left and right of a common control and address bus, respectively. Memory modules of a first group are loaded in the data buses of the first channel and memory modules of a second group are loaded in the data buses of the second channel. Also, in the memory system, the memory modules share the common control and address bus positioned in the center. Also, the memory modules are arranged so that some parts of the memory modules overlap each other and that the memory modules of the first group and the memory modules of the second group cross each other.

Abstract: A socket for mounting memory module boards on a printed circuit board (PCB) includes a first socket, a second socket and a third socket. The first socket includes a first socket body that receives a first memory module board, a first clip that connects to a tab of the first memory module board, and a first signal line connected to the first clip and extending outside of the first socket body. The second socket is in an area adjacent to the first socket and includes a second socket body that receives the first and a second memory module boards on opposite sides of the second socket body, two sets of upper socket pins disposed within the second socket body, and two sets of lower socket pins disposed to be opposite to the upper socket pins.