Patents by Inventor Byung Wook Bae

Byung Wook Bae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140048937
    Abstract: A semiconductor device includes a semiconductor substrate having two surfaces. First side faces second side and includes recesses, and a plurality of through silicon vias (TSV), which penetrate through the semiconductor substrate, are exposed by the recesses. Even when the TSVs have different heights from each other or the degree of back-grinding is changed, due to a process parameters, yield of the semiconductor device is improved by reducing failure caused when a TSV is not exposed.
    Type: Application
    Filed: December 18, 2012
    Publication date: February 20, 2014
    Applicant: SK HYNIX INC.
    Inventor: Byung Wook BAE
  • Publication number: 20140014957
    Abstract: A semiconductor device is provided to check through silicon via (TSV) connectivity at a wafer level. The semiconductor device includes a first metal layer formed over a through silicon via (TSV), a second metal layer and a third metal layer formed at both sides of the first metal layer to be electrically coupled to the TSV, and a fourth metal layer formed over the first metal layer to be electrically coupled to the first metal layer.
    Type: Application
    Filed: September 10, 2012
    Publication date: January 16, 2014
    Applicant: SK hynix Inc.
    Inventor: Byung Wook BAE
  • Patent number: 8629033
    Abstract: A method for manufacturing a semiconductor device prevents a lower electrode from leaning, in a dip-out process of an interlayer insulation film forming a lower electrode. A conductive material of a lower electrode is used as a support layer instead of a conventional nitride film support layer. This prevents a crack from being generated in a nitride film support layer. A method for manufacturing the semiconductor device is also disclosed.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: January 14, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Byung Wook Bae
  • Publication number: 20130078782
    Abstract: A method for manufacturing a semiconductor device prevents a lower electrode from leaning, in a dip-out process of an interlayer insulation film forming a lower electrode. A conductive material of a lower electrode is used as a support layer instead of a conventional nitride film support layer. This prevents a crack from being generated in a nitride film support layer. A method for manufacturing the semiconductor device is also disclosed.
    Type: Application
    Filed: January 10, 2012
    Publication date: March 28, 2013
    Applicant: Hynix Semiconductor Inc.
    Inventor: Byung Wook BAE
  • Patent number: 8405483
    Abstract: A fuse used in a semiconductor memory device. The fuse is formed with a “X” shape where one circuit may be connected simultaneously to a plurality of other circuits. As a result, a fuse region is reduced, and the cutting number is also decreased, thereby lowering the possibility of defects resulting from cutting errors.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: March 26, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jeong Soo Kim, Byung Wook Bae
  • Patent number: 8217710
    Abstract: The invention relates to a semiconductor device comprising a fuse that is implemented as a bar type pattern that forms a straight line instead of a pattern that is difficult to secure a manufacturing margin. A fuse block including a plurality of fuses comprises a plurality of first connection parts, each including a blowing area, a plurality of second connection parts, wherein the plurality of the second connection parts and the plurality of the corresponding first connection parts respectively form part of the fuse, and a common connection unit configured to electrically connect the plurality of the first connection parts and the plurality of the second connection parts.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: July 10, 2012
    Assignee: Hynix Semiconductor Inc
    Inventor: Byung Wook Bae
  • Publication number: 20110001211
    Abstract: Provided is a fuse of a semiconductor device that includes a Y type fuse and an insulation layer configured to expose the Y type fuse such that an exposed portion of the Y type fuse has a substantially ‘V’ shape. According to the present invention, metal crack is prevented from occurring in a Y type fuse under a high temperature and high humidity condition of a reliability test so that the reliability and competitiveness of semiconductor devices can be improved.
    Type: Application
    Filed: December 17, 2009
    Publication date: January 6, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventor: Byung Wook BAE
  • Publication number: 20100225381
    Abstract: The invention relates to a semiconductor device comprising a fuse that is implemented as a bar type pattern that forms a straight line instead of a pattern that is difficult to secure a manufacturing margin. A fuse block including a plurality of fuses comprises a plurality of first connection parts, each including a blowing area, a plurality of second connection parts, wherein the plurality of the second connection parts and the plurality of the corresponding first connection parts respectively form part of the fuse, and a common connection unit configured to electrically connect the plurality of the first connection parts and the plurality of the second connection parts.
    Type: Application
    Filed: December 30, 2009
    Publication date: September 9, 2010
    Applicant: Hynix Semiconductor Inc.
    Inventor: Byung Wook BAE
  • Publication number: 20100090791
    Abstract: A fuse used in a semiconductor memory device. The fuse is formed with a “X” shape where one circuit may be connected simultaneously to a plurality of other circuits. As a result, a fuse region is reduced, and the cutting number is also decreased, thereby lowering the possibility of defects resulting from cutting errors.
    Type: Application
    Filed: December 23, 2008
    Publication date: April 15, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Jeong Soo Kim, Byung Wook Bae