Abstract: The present disclosure relates to the field of display technology, and provides a shift register unit and a driving method thereof, a gate driving circuit, and a display panel. The shift register unit includes: an input circuit, a charging circuit, an inverter circuit, an output circuit, and a pull-down circuit. The input circuit is connected to a second clock signal terminal, a signal input terminal and a first node. The inverter circuit is connected to the signal input terminal, the second clock signal terminal, a first power supply terminal, a second power supply terminal and a pull-down node. The output circuit is connected to the pull-up node, the first power supply terminal and an output terminal. The pull-down circuit is connected to the pull-down node, the second power supply terminal, the pull-up node, and the output terminal.

Abstract: A pixel circuit and a driving method thereof, and a display device, the pixel circuit being configured to drive a light-emitting element and including: a node control sub-circuit, which is configured to provide a first node with a signal of a data signal end and provide a second node with a signal of a control signal end under the control of a first scanning end; a driving sub-circuit, which is configured to provide the second node with a driving current under the control of the first node and the second node; a storage sub-circuit, which is configured to store electric charge between the first node and the second node; a reading sub-circuit, and the light-emitting element, which is electrically connected to the second node and a second power supply end, respectively.

Abstract: Pixel driving method for driving pixel unit, display driving method and display substrate are provided. The pixel unit includes pixel driving circuit, including driving transistor, storage capacitor, and data writing circuit, the driving transistor has control electrode coupled to first terminal of the data writing circuit and the storage capacitor, and first electrode coupled to second terminal of the storage capacitor, and second terminal of the data writing circuit is coupled to data line. The pixel driving method includes: loading a data voltage into the data line, and controlling the first and second terminals of the data writing circuit to be connected; controlling the data line to be floating, and maintaining connection between the first and second terminals of the data writing circuit to reduce gate-source voltage of the driving transistor; and controlling the first and second terminals of the data writing circuit to be disconnected.

Abstract: A shift register unit, a driving method, a gate driving circuit, and a display device are disclosed. The shift register unit includes: a shift circuit, used to output, to a first output end during a first time period, a power control signal, and output the power control signal to a second output end during a second time period; and a signal integrated circuit, used to output the power control signal to a third output end in response to the power control signal and a first output signal, output the power control signal to the third output end in response to the power control signal and a second output signal, and output, to the third output end at times other than the first and second time period in response to the power control signal, the first output signal and the second output signal, a first pull-down power signal.

Abstract: Shift register includes signal writing circuit, voltage control circuit and output circuit. The signal writing circuit is configured to write inverted signal of input signal provided by signal input terminal into second node responsive to control of second clock signal provided by second clock signal terminal. The voltage control circuit is configured to write first operating voltage into first node and write second clock signal into third node in voltage control circuit in response to control of voltage at first node, write second operating voltage into third node in response to control of second clock signal and write first clock signal provided by first clock signal terminal into first node in response to control of voltage at third node and first clock signal. The output circuit is configured to write second or first operating voltage into signal output terminal in response to control of voltage at first or second node.

Abstract: An array substrate and a detection method thereof, and a display panel are disclosed. The array substrate includes a plurality of subpixels and a plurality of detection line structures. The plurality of subpixels are arranged in an array of a plurality of rows and a plurality of columns along a first direction and a second direction. Each of the plurality of detection line structures includes at least one first detection line extending along the first direction; adjacent (n)th row and (n+1)th row of subpixels in the array form a subpixel row group, one detection line structure is provided between the (n)th row and (n+1)th row of subpixels in each subpixel row group, and the detection line structure is configured to be connected to the (n)th row and (n+1)th row of subpixels and detect electrical characteristics of first transistors or light-emitting elements in the subpixels.

Abstract: A thin film transistor structure and a manufacturing method thereof, a circuit structure, a display substrate and a display device are provided. The thin film transistor structure includes: a base plate, and a first thin film transistor and a second thin film transistor stacked on the base plate. The first thin film transistor and the second thin film transistor share a same active layer.

Abstract: Pixel driving method for driving pixel unit display driving method and display substrate are provided. The pixel unit includes pixel driving circuit, including driving transistor, storage capacitor, and data writing circuit, the driving transistor has control electrode coupled to first terminals of the data writing circuit and the storage capacitor, and first electrode coupled to second terminal of the storage capacitor, and second terminal of the data writing circuit is coupled to data line. The pixel driving method includes: loading a data voltage into the data line, and controlling the first and second terminals of the data writing circuit to be connected; controlling the data line to be floating, and maintaining connection between the first and second terminals of the data writing circuit to reduce gate-source voltage of the driving transistor; and controlling the first and second terminals of the data writing circuit to be disconnected.

Abstract: A display region includes a plurality of pixel driving circuitry setting regions arranged sequentially in a first direction, and each pixel driving circuitry setting region extends in a second direction intersecting the first direction. Each display circuitry includes a plurality of subpixels in one-to-one correspondence with the pixel driving circuitry setting regions, each subpixel includes a subpixel driving circuitry and a light-emitting element coupled to each other, the subpixel driving circuitry is located in a corresponding pixel driving circuitry setting region, the light-emitting element is located at a side of the subpixel driving circuitry away from the substrate, a width of the light-emitting element is greater than a width of the corresponding pixel driving circuitry setting region in the first direction, and a length of the light-emitting element is smaller than a length of the corresponding pixel driving circuitry setting region in the second direction.

Abstract: A display panel and a fabricating method thereof, and a displaying device. The display panel includes a substrate, a resistance reducing trace, an inter-layer-medium layer and a signal line. The substrate is divided into a plurality of sub-pixel regions and a pixel separating region. The resistance reducing trace is provided on the pixel separating region of the substrate. The inter-layer-medium layer is provided on the substrate, and the inter-layer-medium layer has an opening exposing the resistance reducing trace. The signal line is provided within the opening, the signal line is connected to the resistance reducing trace, the signal line is distributed in a column direction along the display panel, and in a row direction along the display panel, a width of the opening is greater than or equal to a width of the signal line.

Abstract: A display substrate includes: a base substrate including a display area and a peripheral area pixel units in the display area, each including a pixel drive circuit and a light emitting device the light emitting device including a first electrode, a second electrode, and a light emitting layer; a first power trace located in the peripheral area and electrically connected to the first electrode; a second power trace located in the peripheral area and electrically connected to the second electrode; a planarization layer with at least a portion thereof being located in the peripheral area. An orthographic projection of the planarization layer on the base substrate at least partially overlaps an orthographic projection of each of the first and second power traces on the base substrate, the first and second power traces are located in different layers, and a portion of the planarization layer is located between the first and second power traces.

Abstract: An array substrate includes a base substrate (1); a driving transistor (2) on the base substrate (1); an insulating layer (3) on the driving transistor (2), the insulating layer (3) comprising a via hole above a first electrode (21) of the driving transistor (2); a conductive portion (4) on the insulating layer (3); and a light emitting device (6) on the conductive portion (4) and electrically connected to the conductive portion (4). The conductive portion (4) may be electrically connected to the first electrode (21) of the driving transistor (2) through the via hole. The light emitting device (6) may be above the via hole, and an orthographic projection of the light emitting device (6) on the base substrate (1) may cover an orthographic projection of the via hole on the base substrate (1).

Abstract: The embodiments of the present disclosure propose a shift register and a method for driving the same, a gate driving circuit, and a display apparatus. The shift register includes: a scanning circuit configured to generate a first signal for causing a gate driving signal output by the shift register to have a row shift portion during a scanning period; a sensing circuit configured to generate a second signal for causing the gate driving signal to have a frame shift portion during a blanking period; and a random shift circuit electrically coupled to the scanning circuit and the sensing circuit respectively, and configured to generate the gate driving signal having the row shift portion and randomly having the frame shift portion based on the first signal and the second signal.

Abstract: Provided are a pixel structure, a display panel and a control method thereof. The pixel structure includes four sub-pixel units, wherein the i-th sub-pixel unit includes: an i-th element to be driven and an i-th drive circuit, 1?i?4, and the i-th drive circuit is respectively connected with an M-th data line and an N-th scanning line, and is configured to drive the i-th element to be driven according to a data signal of the M-th data line under control of the N-th scanning line, M = { 1 , 1 ? i ? 2 2 , 3 ? i ? 4 , N = { 1 , 2 ? i ? 3 2 , i ? ? is ? ? 1 ? ? or ? ? 4 .

Abstract: An array substrate, a display panel and a display device are provided. The array substrate includes a plurality of pixel units arranged in an array, each pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel, and each of the first, second and third sub-pixels includes a pixel circuit including a switching transistor, a driving transistor, a sensing transistor, a storage capacitor and a light-emitting device. The first sub-pixels, the second sub-pixels and the third sub-pixels included in each row of the array are controlled by four scanning lines, and at least one of the four scanning lines is shared by the row of the array and another row of the array adjacent to the row of the array. Each column of pixel units of the array are coupled to a same data line.

Abstract: A display device and a display panel (1) thereof, and a display panel (1) manufacturing method. The display panel (1) comprises: a substrate (10) and a light-emitting structure (20) located on the substrate (10). A pixel driving circuit (30) exists between the substrate (10) and the light-emitting structure (20) and comprises a storage capacitor (Cst); an orthogonal projection of the storage capacitor (Cst) on the substrate (10) at least partially overlaps an orthogonal projection of the light-emitting structure (20) on the substrate (10); the storage capacitor (Cst) comprises a first transparent polar plate (311) proximate to the substrate (10) and a second transparent polar plate (312) distant from the substrate (10); an orthogonal projection of the first transparent polar plate (311) on the substrate (10) is located within an orthogonal projection of the second transparent polar plate (312) on the substrate (10).

Abstract: A display panel and a display device are disclosed. The display panel includes a plurality of sub-pixel units arranged in an array, and the array includes N rows and 8M columns. Sub-pixel units in each row are divided into a plurality of sub-pixel unit groups, and each sub-pixel unit group includes a first sub-pixel unit, a second sub-pixel unit, a third sub-pixel unit, a fourth sub-pixel unit, a fifth sub-pixel unit, a sixth sub-pixel unit, a seventh sub-pixel unit and an eighth sub-pixel unit which are sequentially in eight adjacent columns along a first direction.

Abstract: A display substrate, manufacturing method thereof, and display device. The display substrate comprises: a substrate, gate line, data line, power connection line and multiple sub-pixels on the substrate, the display substrate has defective points formed by short-circuiting of the gate line and data line, and the gate line forming defective points is a defective gate line; the data line forming defective points is a defective data line; the power connection line is arranged on the same layer as gate electrodes of multiple transistors; the defective gate line and defective power connection line are disconnected, the display substrate further comprises: a repair line disposed on one side, away from the substrate, of the source drain electrode of multiple transistors, the repair line is respectively connected to the partially disconnected defective gate line and partially disconnected defective power connection line, and is used for transmitting scanning signals to repair the display substrate.

Abstract: A pixel unit includes a first sub-pixel circuit and a second sub-pixel circuit. The first sub-pixel circuit includes a first sub-pixel driving circuit and a first light-emitting element, and the second sub-pixel circuit includes a second sub-pixel driving circuit and a second light-emitting element. The first sub-pixel driving circuit and the second sub-pixel driving circuit are connected to a first data line, and the first sub-pixel driving circuit is connected to a first gate line, the second sub-pixel driving circuit is connected to the second gate line. The first sub-pixel driving circuit is configured to drive the first light-emitting element by a data voltage on the first data line under the control of the first gate line. The second sub-pixel driving circuit is configured to drive the second light-emitting element by the data voltage on the first data line under the control of the second gate line.

Abstract: The present disclosure discloses a shift register and a driving method therefor, a gate drive circuit, and a display device. An input circuit is configured to respond to a signal of an input signal end and provide a signal of a first reference signal terminal to a first node; a reset circuit is configured to respond to the signal of the second node and provide a signal of a second reference signal end to the first node; and an output circuit is configured to respond to the signal of the first node and provide the signal of the clock signal end to an output signal end and is configured to respond to the signal of the third node and provide the signal of the second reference signal end to the output signal end.