Patents by Inventor Carl J. Radens
Carl J. Radens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9348680Abstract: A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.Type: GrantFiled: April 1, 2014Date of Patent: May 24, 2016Assignee: International Business Machines CorporationInventors: Rajiv V. Joshi, Rouwaida N. Kanj, Sani R. Nassif, Carl J. Radens
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Publication number: 20160126249Abstract: A plurality of fin structures containing, from bottom to top, a non-doped semiconductor portion and a second doped semiconductor portion of a first conductivity type, extend upwards from a surface of a first doped semiconductor portion of the first conductivity type. A trapping material (e.g., an electron-trapping material) is present along a bottom portion of sidewall surfaces of each non-doped semiconductor portion and on exposed portions of each first doped semiconductor portion. Functional gate structures straddle each fin structure. Metal lines are located above each fin structure and straddle each functional gate structure. Each metal line is orientated perpendicular to each functional gate structure and has a bottommost surface that is in direct physical contact with a portion of a topmost surface of each of the second doped semiconductor portions.Type: ApplicationFiled: October 29, 2014Publication date: May 5, 2016Inventors: Ramachandra Divakaruni, Arvind Kumar, Carl J. Radens
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Patent number: 9324793Abstract: An ashing chemistry employing a combination of Cl2 and N2 is provided, which removes residual material from sidewalls of a patterned metallic hard mask layer without residue such that the sidewalls of the patterned metallic hard mask layer are vertical. The vertical profiled of the sidewalls of the patterned metallic hard mask layer can be advantageously employed to reduce pattern factor dependency in the etch bias between the pattern transferred into an underlying layer and the pattern as formed on the metallic hard mask layer. Further, the ashing chemistry can be employed to enhance removal of stringers in vertical portions of a metallic material layer.Type: GrantFiled: September 30, 2015Date of Patent: April 26, 2016Assignees: International Business Machines Corporation, STMICROELECTRONICS, INC.Inventors: Lawrence A. Clevenger, Carl J. Radens, Richard S. Wise, Edem Wornyo, Yiheng Xu, John Zhang
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Patent number: 9305930Abstract: A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.Type: GrantFiled: December 11, 2013Date of Patent: April 5, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Ramachandra Divakaruni, Arvind Kumar, Carl J. Radens
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Patent number: 9257433Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.Type: GrantFiled: June 11, 2015Date of Patent: February 9, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Herbert L. Ho, Naoyoshi Kusaba, Karen A. Nummy, Carl J. Radens, Ravi M. Todi, Geng Wang
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Publication number: 20160020105Abstract: An ashing chemistry employing a combination of Cl2 and N2 is provided, which removes residual material from sidewalls of a patterned metallic hard mask layer without residue such that the sidewalls of the patterned metallic hard mask layer are vertical. The vertical profiled of the sidewalls of the patterned metallic hard mask layer can be advantageously employed to reduce pattern factor dependency in the etch bias between the pattern transferred into an underlying layer and the pattern as formed on the metallic hard mask layer. Further, the ashing chemistry can be employed to enhance removal of stringers in vertical portions of a metallic material layer.Type: ApplicationFiled: September 30, 2015Publication date: January 21, 2016Inventors: Lawrence A. Clevenger, Carl J. Radens, Richard S. Wise, Edem Wornyo, Yiheng Xu, John Zhang
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Patent number: 9209036Abstract: An ashing chemistry employing a combination of Cl2 and N2 is provided, which removes residual material from sidewalls of a patterned metallic hard mask layer without residue such that the sidewalls of the patterned metallic hard mask layer are vertical. The vertical profiled of the sidewalls of the patterned metallic hard mask layer can be advantageously employed to reduce pattern factor dependency in the etch bias between the pattern transferred into an underlying layer and the pattern as formed on the metallic hard mask layer. Further, the ashing chemistry can be employed to enhance removal of stringers in vertical portions of a metallic material layer.Type: GrantFiled: February 24, 2014Date of Patent: December 8, 2015Assignees: International Business Machines Corporation, STMICROELECTRONICS, INC.Inventors: Lawrence A. Clevenger, Carl J. Radens, Richard S. Wise, Edem Wornyo, Yiheng Xu, John Zhang
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Patent number: 9196707Abstract: At least one layer including a scavenging material and a dielectric material is deposited over a gate stack, and is subsequently anisotropically etched to form a oxygen-scavenging-material-including gate spacer. The oxygen-scavenging-material-including gate spacer can be a scavenging-nanoparticle-including gate spacer or a scavenging-island-including gate spacer. The scavenging material is distributed within the oxygen-scavenging-material-including gate spacer in a manner that prevents an electrical short between a gate electrode and a semiconductor material underlying a gate dielectric. The scavenging material actively scavenges oxygen that diffuses toward the gate dielectric from above, or from the outside of, a dielectric gate spacer that can be formed around the oxygen-scavenging-material-including gate spacer.Type: GrantFiled: November 6, 2013Date of Patent: November 24, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Deleep R. Nair, Vijay Narayanan, Carl J. Radens, Jay M. Shah
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Publication number: 20150287809Abstract: Semiconductor fins are formed on a top surface of a substrate. A dielectric material is deposited on the top surfaces of the semiconductor fins and the substrate by an anisotropic deposition. A dielectric material layer on the top surface of the substrate is patterned so that the remaining portion of the dielectric material layer laterally surrounds each bottom portion of at least one semiconductor fin, while not contacting at least one second semiconductor fin. Dielectric material portions on the top surfaces of the semiconductor fins may be optionally removed. Each first semiconductor fin has a lesser channel height than the at least one second semiconductor fin. The first and second semiconductor fins can be employed to provide fin field effect transistors having different channel heights.Type: ApplicationFiled: October 21, 2014Publication date: October 8, 2015Inventors: Pranita Kerber, Carl J. Radens, Sudesh Saroop
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Publication number: 20150287743Abstract: Semiconductor fins are formed on a top surface of a substrate. A dielectric material is deposited on the top surfaces of the semiconductor fins and the substrate by an anisotropic deposition. A dielectric material layer on the top surface of the substrate is patterned so that the remaining portion of the dielectric material layer laterally surrounds each bottom portion of at least one semiconductor fin, while not contacting at least one second semiconductor fin. Dielectric material portions on the top surfaces of the semiconductor fins may be optionally removed. Each first semiconductor fin has a lesser channel height than the at least one second semiconductor fin. The first and second semiconductor fins can be employed to provide fin field effect transistors having different channel heights.Type: ApplicationFiled: April 2, 2014Publication date: October 8, 2015Applicant: International Business Machines CorporationInventors: Pranita Kerber, Carl J. Radens, Sudesh Saroop
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Publication number: 20150279844Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.Type: ApplicationFiled: June 11, 2015Publication date: October 1, 2015Inventors: Herbert L. Ho, Naoyoshi Kusaba, Karen A. Nummy, Carl J. Radens, Ravi M. Todi, Geng Wang
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Publication number: 20150279843Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.Type: ApplicationFiled: June 11, 2015Publication date: October 1, 2015Inventors: Herbert L. Ho, Naoyoshi Kusaba, Karen A. Nummy, Carl J. Radens, Ravi M. Todi, Geng Wang
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Patent number: 9147031Abstract: Systems and methods for determining a chip yield are disclosed. One system includes a first level integration solver and a second level integration solver. The first level integration solver is configured to obtain a first probability distribution function modeling variations within a chip and to perform a discontinuous first level integration with the first probability distribution function. In addition, the second level integration solver is implemented by a hardware processor and is configured to perform a continuous second level integration based on a second probability distribution function modeling variations between dies to determine the chip yield.Type: GrantFiled: January 31, 2013Date of Patent: September 29, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Carl J. Radens, Amith Singhee
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Publication number: 20150243510Abstract: An ashing chemistry employing a combination of Cl2 and N2 is provided, which removes residual material from sidewalls of a patterned metallic hard mask layer without residue such that the sidewalls of the patterned metallic hard mask layer are vertical. The vertical profiled of the sidewalls of the patterned metallic hard mask layer can be advantageously employed to reduce pattern factor dependency in the etch bias between the pattern transferred into an underlying layer and the pattern as formed on the metallic hard mask layer. Further, the ashing chemistry can be employed to enhance removal of stringers in vertical portions of a metallic material layer.Type: ApplicationFiled: February 24, 2014Publication date: August 27, 2015Applicants: STMicroelectronics, Inc., International Business Machines CorporationInventors: Lawrence A. Clevenger, Carl J. Radens, Richard S. Wise, Edem Wornyo, Yiheng Xu, John Zhang
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Patent number: 9087784Abstract: A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) is provided. Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack may also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein.Type: GrantFiled: January 29, 2014Date of Patent: July 21, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Dechao Guo, Siddarth A. Krishnan, Unoh Kwon, Carl J. Radens, Shahab Siddiqui
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Patent number: 9089080Abstract: Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.Type: GrantFiled: June 7, 2013Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Timothy J. Dalton, Elbert E. Huang, Sampath Purushothaman, Carl J. Radens
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Publication number: 20150200276Abstract: After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.Type: ApplicationFiled: January 16, 2014Publication date: July 16, 2015Applicant: International Business Machines CorporationInventors: Kangguo Cheng, Ramachandra Divakaruni, Carl J. Radens
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Patent number: 9082625Abstract: Embodiments of present invention provide a method of forming device pattern. The method includes defining a device pattern to be created in a device layer; forming a sacrificial layer on top of the device layer; identifying an imprinting mold that, at a position along a height thereof, has a horizontal cross-sectional shape that represents the device pattern; pushing the imprinting mold uniformly into the sacrificial layer until at least the position of the imprinting mold reaches a level inside the sacrificial layer that is being pushed by the imprinting mold; removing the imprinting mold away from the sacrificial layer; forming a hard mask in recesses created by the imprinting mold in the sacrificial layer, the hard mask has a pattern representing the device pattern; and transferring the pattern of the hard mask into underneath the device layer.Type: GrantFiled: December 11, 2013Date of Patent: July 14, 2015Assignees: International Business Machines Corporation, STMICROELECTRONICS, Inc.Inventors: Lawrence A. Clevenger, Carl J. Radens, Richard S. Wise, Yiheng Xu, John Zhang
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Patent number: 9059000Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.Type: GrantFiled: April 21, 2008Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Deok-kee Kim, Kenneth T. Settlemyer, Jr., Kangguo Cheng, Ramachandra Divakaruni, Carl J. Radens, Dirk Pfeiffer, Timothy Dalton, Katherina Babich, Arpan P. Mahorowala, Harald Okorn-Schmidt
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Patent number: 9059320Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.Type: GrantFiled: February 29, 2012Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Herbert L. Ho, Naoyoshi Kusaba, Karen A. Nummy, Carl J. Radens, Ravi M. Todi, Geng Wang