Abstract: A hybrid CMOS-bipolar memory cell for a high speed memory includes a CMOS latch which has two storage nodes (104) and (106) for storing two logic states. The CMOS latch is disposed between a high voltage node (110) and a low voltage node (114). The two nodes are maintained at a predetermined voltage to maintain a static state. A bipolar current drive transistor (120) is provided which is connected to one of the storage nodes (106) to provide a low source impedance for output from the memory cell. A work line (44) is connected to the high voltage node (110) for selection thereof by varying between two predetermined voltages. The cell is written to be selectively discharging either node (104) or (106) to a low voltage node (114) through bipolar transistors (122) and (124). The bipolar transistor (122) and (124) provide high transconductance switches for selectively discharging the storage nodes (104) and (106).

Abstract: A single-level multiplexer (70) has a plurality of stages (72-78), one for each bit. In each stage, a select transistor (84) has a current path coupling an output node (86) to a common node (88), and a control element that is coupled to a select signal line (80). A data transistor (90) has a current path connecting a voltage supply (92) to the common node (88), and a control element connected to a data signal source (82). Common node (88) is connected to a current source (94, 96, 98, 100). The output node (86) of each stage is coupled together with the output nodes of the other states to an output (108) of the multiplexer.

Abstract: A hybrid ECL memory includes a hybrid memory array 36 which utilizes cross coupled CMOS latches (70). Each CMOS latch (70) is accessed by an ECL decoder (40) and an ECL Word Line driver (42) to read data therefrom. Data is accessed through a bipolar transistor (120) for output to an ECL sense amp. The column select operation is provided by an ECL decoder (50) to select both the Read and the Write operation. The Write operation is provided with emitter coupled logic by pulling up one of the storage nodes in the CMOS latch (70) with a low source impedance PNP transistor (122). Selection is provided by varying the Word Line between two voltages through a low source impedance transistor (78) with the voltages being ECL compatible.

Abstract: A semiconductor memory includes a memory cell (42) which utilizes a cross-coupled bipolar SCR latch. The latch includes two sense nodes (78) and (80). Sense node (78) has associated therewith an NPN transistor (82) and a PNP load transistor (84). Similarly, sense node (80) has associated therewith an NPN transistor (90) and a PNP load transistor (92) configured as an SCR. Each of these sense nodes is cross-coupled to the base of the NPN transistor connected to the opposite sense node. A forward biased PN junction is connected between an external Write circuit and the collector of each of the NPN transistors to provide an independent current path when changing from a low logic state to a high logic state. This decreases the recovery time when going from a saturated to a cut-off state for the NPN transistor.

Abstract: A fast write CMOS memory cell includes two CMOS inverters connected in a latched configuration with the first CMOS inverter having a P-channel transistor (98) and an N-channel transistor (102) and the second inverter having a P-channel transistor (90) and an N-channel transistor (96). The output of the first inverter is connected to the input of the second inverter with the output of the second inverter connected to the input of the first inverter through a pass transistor (104). The pass transistor (104) is conductive during the static mode of operation and is nonconductive during the write operation. During write, the input of the first inverter is forced to a predetermined logic state with the pass transistor (104) nonconductive. After write, the pass transistor (104) conducts and reconfigures the latch.

Abstract: A multiport random access memory cell includes a current mode latch (68) for storing two logic states and interface circuits for interfacing the input of the latch (68) with multiple input ports and the output of the latch (68) with multiple output ports. The interface circuitry comprises current switches (70-76) for switching current to a current source in the presence of a write select and a row select signal to override the holding current in the current mode latch. The output interface circuitry includes current sensors (78-84) for sensing the logic state in the latch and outputting it to the select output ports in the presence of a row select signal. The current switches and the current sensors utilize current mode logic and with a common current source. The current source is disable in the absence of any row select signal such that power is not drawn by the memory cell in the unselected state.