Patents by Inventor Carlos A. Mazure

Carlos A. Mazure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7407867
    Abstract: A method for producing a semiconductor structure that includes at least one useful layer on a substrate.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: August 5, 2008
    Assignees: S.O.I.Tec Silicon on Insulator Technologies, Commissariat à l'Energie Atomique (CEA)
    Inventors: Bruno Ghyselen, Cécile Aulnette, Benoĩt Bataillou, Carlos Mazure, Hubert Moriceau
  • Patent number: 7407869
    Abstract: A method for manufacturing a free-standing substrate made of a semiconductor material. A first assembly is provided and it includes a relatively thinner nucleation layer of a first material, a support of a second material, and a removable bonding interface defined between facing surfaces of the nucleation layer and support. A substrate of a relatively thicker layer of a third material is grown, by epitaph on the nucleation layer, to form a second assembly with the substrate attaining a sufficient thickness to be free-standing. The third material is preferably a monocrystalline material. Also, the removable character of the bonding interface is preserved with at least the substrate being heated to an epitaxial growth temperature.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: August 5, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruno Ghyselen, Fabrice Letertre, Carlos Mazure
  • Patent number: 7387947
    Abstract: The present invention relates to a method for transferring a thin useful layer from a donor substrate having an ordered crystalline structure to a receiver substrate. The method includes creation of a weakened zone in the donor substrate to define the layer to be transferred from the donor substrate. The crystalline structure of a surface region of the donor substrate is disturbed so as to create a disturbed superficial region within the thickness of the donor substrate, and thus define a disturbance interface between the disturbed superficial region and a subjacent region of the donor substrate for which the crystalline structure remains unchanged. Next, the donor substrate is subjected to a recrystallization annealing in order to at least partial recrystallize of the disturbed region, starting from the crystalline structure of the subjacent region of the donor substrate, and to create a zone of crystalline defects in the plane of the disturbance interface.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: June 17, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Ian Cayrefourcq, Carlos Mazure, Konstantin Bourdelle
  • Publication number: 20080102601
    Abstract: This invention relates to a method for producing a substrate by transferring a layer of a material from a donor substrate to a support substrate, and then by removing a part of the layer of material to form the thin layer. The step of removing a part of the layer of material to form the thin layer comprises forming an amorphous layer in a part of the thin layer, and then recrystallizing the amorphous layer.
    Type: Application
    Filed: October 23, 2007
    Publication date: May 1, 2008
    Inventors: Konstantin Bourdelle, Carlos Mazure
  • Publication number: 20080014712
    Abstract: The invention provides methods of direct bonding substrates at least one of which includes a layer of semiconductor material that extends over its front face or in the proximity thereof. The provided methods include, prior to bonding, subjecting the bonding face of at least one substrate comprising a semiconductor material to selected heat treatment at a selected temperature and in a selected gaseous atmosphere. The bonded substrates are useful for electronic, optic, or optoelectronic applications.
    Type: Application
    Filed: January 17, 2007
    Publication date: January 17, 2008
    Inventors: Konstantin Bourdelle, Carlos Mazure, Olivier Rayssac, Pierre Rayssac, Gisele Rayssac
  • Publication number: 20080014714
    Abstract: A method of fabricating a hybrid substrate by direct bonding of donor and receiver substrates where each substrate has a respective front face and surface, with the front face of the receiver substrate having a semiconductor material near the surface, and the donor substrate including a zone of weakness that defines a layer to be transferred. The method includes preparing the substrate surfaces by exposing the surface of the receiver substrate to a temperature from about 900° C. to about 1200° C. in an inert atmosphere for at least 30 sec; directly bonding together the front faces of the prepared substrates to form a composite substrate; heat treating the composite substrate to increase bonding strength between the front surfaces of the donor and receiver substrates; and transferring the layer from the donor substrate by detaching the remainder of the donor substrate at the zone of weakness.
    Type: Application
    Filed: August 1, 2007
    Publication date: January 17, 2008
    Inventors: Konstantin BOURDELLE, Carlos Mazure, Olivier Rayssac, Pierre Rayssac, Gisele Rayssac
  • Publication number: 20070264801
    Abstract: Pile ups of threading dislocations in thick graded buffer layer are reduced by enhancing dislocation gliding. During formation of a graded SiGe buffer layer, deposition of SiGe from a silicon precursor and a germanium precursor is interrupted one or more times with periods in which the flow of the silicon precursor to the substrate is stopped while the flow of the germanium precursor to the substrate is maintained.
    Type: Application
    Filed: May 9, 2006
    Publication date: November 15, 2007
    Inventors: Nyles Cody, Chantal Arena, Pierre Tomasini, Carlos Mazure
  • Patent number: 7232743
    Abstract: A method for fabricating a semiconductor structure having a high-strained crystalline layer with a low crystal defect density is disclosed. The structure includes a substrate having a first material comprising germanium or a Group(III)-Group(V)-semiconductor or alloy thereof. In addition, a crystalline epitaxial first layer, comprising a graded buffer layer and a substantially relaxed layer, is provided. The buffer layer is sufficiently relaxed to provide relaxation of the substantially relaxed layer deposited thereon. A further layer may be provided on the first layer, and the transfer of at least the further layer is facilitated by providing a weakened zone in the first layer.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: June 19, 2007
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Cécile Aulnette, Frédéric Dupont, Carlos Mazuré
  • Publication number: 20070023867
    Abstract: The invention relates to a method of producing a film intended for applications in electronics, optics or optronics starting from an initial wafer, which includes a step of implanting atomic species through one of the faces of the wafer. This method includes forming a step of defined height around the periphery of the wafer, with the step having a mean thickness that is less than that of the wafer; and selectively implanting atomic species through a face of the wafer but not through the step to form an implanted zone at a defined implant depth with the film being defined between the face of the wafer and the implanted zone. The implantation of atomic species into the step can be prevented by forming a protective layer at least over the step or by masking the step. The invention also relates to a wafer obtainable by the method.
    Type: Application
    Filed: September 6, 2005
    Publication date: February 1, 2007
    Inventors: Cecile Aulnette, Ian Cayrefourcq, Carlos Mazure
  • Publication number: 20060286770
    Abstract: A method for producing a semiconductor structure that includes at least one useful layer on a substrate.
    Type: Application
    Filed: August 24, 2006
    Publication date: December 21, 2006
    Applicants: S.O.I.Tec Silicon on Insulator Technologies S.A., Commissariat à l'Energie Atomique (CEA)
    Inventors: Bruno Ghyselen, Cecile Aulnette, Benoit Bataillou, Carlos Mazure, Hubert Moriceau
  • Publication number: 20060220129
    Abstract: The invention relates to a silicon-on-insulator-type multilayer structure that includes a support layer, at least two working layers having different crystalline orientations, and an insulating layer extending over at least a portion of the support layer. This insulating layer extends over the whole surface of the support layer so as to extend completely between the support layer and the working layers. A process for manufacturing such a structure is also provided.
    Type: Application
    Filed: January 27, 2006
    Publication date: October 5, 2006
    Inventors: Fabrice Letertre, Carlos Mazure
  • Patent number: 7115481
    Abstract: A method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate. The method includes providing an initial structure that includes a useful layer having a front face on a support substrate. Atomic species are implanted into the useful layer to a controlled mean implantation depth to form a zone of weakness within the useful layer that defines first and second useful layers. Next, a stiffening substrate is bonded to the front face of the initial structure. The first useful layer is then detached from the second useful layer along the zone of weakness to obtain a pair of semiconductor structures with a first structure including the stiffening substrate and the first useful layer and a second structure including the support substrate and the second useful layer. The structures obtained can be used in the fields of electronics, optoelectronics or optics.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: October 3, 2006
    Assignees: S.O.I.Tec Silicon on Insulator Technologies S.A., Commissariat à l'Energie Atomique (CEA)
    Inventors: Bruno Ghyselen, Cécile Aulnette, Benoit Bataillou, Carlos Mazure, Hubert Moriceau
  • Publication number: 20060128117
    Abstract: A method for forming a relaxed or pseudo-relaxed useful layer on a substrate is described. The method includes growing a strained semiconductor layer on a donor substrate, bonding a receiver substrate to the strained semiconductor layer by a vitreous layer of a material that becomes viscous above a certain viscosity temperature to form a first structure. The method further includes detaching the donor substrate from the first structure to form a second structure comprising the receiver substrate, the vitreous layer, and the strained layer, and then heat treating the second structure at a temperature and time sufficient to relax strains in the strained semiconductor layer and to form a relaxed or pseudo-relaxed useful layer on the receiver substrate.
    Type: Application
    Filed: February 2, 2006
    Publication date: June 15, 2006
    Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Bruno Ghyselen, Carlos Mazure, Emmanuel Arene
  • Publication number: 20060099779
    Abstract: The present invention relates to a method for transferring a thin useful layer from a donor substrate having an ordered crystalline structure to a receiver substrate. The method includes creation of a weakened zone in the donor substrate to define the layer to be transferred from the donor substrate. The crystalline structure of a surface region of the donor substrate is disturbed so as to create a disturbed superficial region within the thickness of the donor substrate, and thus define a disturbance interface between the disturbed superficial region and a subjacent region of the donor substrate for which the crystalline structure remains unchanged. Next, the donor substrate is subjected to a recrystallization annealing in order to at least partial recrystallize of the disturbed region, starting from the crystalline structure of the subjacent region of the donor substrate, and to create a zone of crystalline defects in the plane of the disturbance interface.
    Type: Application
    Filed: December 16, 2005
    Publication date: May 11, 2006
    Inventors: Ian Cayrefourcq, Carlos Mazure, Konstantin Bourdelle
  • Publication number: 20060088979
    Abstract: A method for fabricating a semiconductor structure having a high-strained crystalline layer with a low crystal defect density is disclosed. The structure includes a substrate having a first material comprising germanium or a Group(III)-Group(V)-semiconductor or alloy thereof. In addition, a crystalline epitaxial first layer, comprising a graded buffer layer and a substantially relaxed layer, is provided. The buffer layer is sufficiently relaxed to provide relaxation of the substantially relaxed layer deposited thereon. A further layer may be provided on the first layer, and the transfer of at least the further layer is facilitated by providing a weakened zone in the first layer.
    Type: Application
    Filed: November 17, 2005
    Publication date: April 27, 2006
    Inventors: Cecile Aulnette, Frederic Dupont, Carlos Mazure
  • Patent number: 7022586
    Abstract: The present invention relates to a method for recycling a substrate that has a residue on its surface and a detachment profile resulting from an implantation process. The method includes removing the residue from the substrate to a level substantially equivalent to that of the detachment profile, thus obtaining a substantially uniform planar surface on the substrate, and then polishing the entire surface of the substrate to eliminate defects.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: April 4, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Christophe Maleville, Fabrice Letertre, Thibaut Maurice, Carlos Mazure, Fredéric Metral
  • Patent number: 7018909
    Abstract: The invention relates to methods of forming a relaxed or pseudo-relaxed layer on a substrate, wherein the relaxed layer may be a semiconductor material. An implementation of the method includes growing an elastically stressed semiconductor material layer on a donor substrate, forming a glassy layer of a viscous material and bonding it to the stressed layer, removing a portion of the donor substrate to form a structure that includes the glassy layer, the stressed layer and a surface layer of donor substrate, and then heat treating the structure at a temperature of at least a viscosity temperature of the glassy layer to relax the stressed layer. The glassy layer can also be bonded to a receiving substrate so that the structure can be transferred thereto. Implementations also relate to structures obtained from the method.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: March 28, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Bruno Ghyselen, Carlos Mazure, Emmanuel Arene
  • Publication number: 20060035440
    Abstract: A method for manufacturing a free-standing substrate made of a semiconductor material. A first assembly is provided and it includes a relatively thinner nucleation layer of a first material, a support of a second material, and a removable bonding interface defined between facing surfaces of the nucleation layer and support. A substrate of a relatively thicker layer of a third material is grown, by epitaxy on the nucleation layer, to form a second assembly with the substrate attaining a sufficient thickness to be free-standing. The third material is preferably a monocrystalline material. Also, the removable character of the bonding interface is preserved with at least the substrate being heated to an epitaxial growth temperature.
    Type: Application
    Filed: August 29, 2005
    Publication date: February 16, 2006
    Inventors: Bruno Ghyselen, Fabrice Letertre, Carlos Mazure
  • Patent number: 6995427
    Abstract: A semiconductor structure having a high-strained crystalline layer with a low crystal defect density and a method for fabricating such a semiconductor structure are disclosed. The structure includes a substrate having a first material comprising germanium or a Group (III)–Group (V)-semiconductor or alloy thereof. In addition, a crystalline epitaxial first layer, comprising a graded buffer layer and a substantially relaxed layer, is provided. The buffer layer is sufficiently relaxed to provide relaxation of the substantially relaxed layer deposited thereon. A further layer may be provided on the first layer, and the transfer of at least the further layer is facilitated by providing a weakened zone in the first layer.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: February 7, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Cécile Aulnette, Frédéric Dupont, Carlos Mazuré
  • Patent number: 6964914
    Abstract: A method for manufacturing a free-standing substrate made of a semiconductor material. A first assembly is provided and it includes a relatively thinner nucleation layer of a first material, a support of a second material, and a removable bonding interface defined between facing surfaces of the nucleation layer and support. A substrate of a relatively thicker layer of a third material is grown, by epitaxy on the nucleation layer, to form a second assembly with the substrate attaining a sufficient thickness to be free-standing. The third material is preferably a monocrystalline material. Also, the removable character of the bonding interface is preserved with at least the substrate being heated to an epitaxial growth temperature.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: November 15, 2005
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Bruno Ghyselen, Fabrice Letertre, Carlos Mazure