Patents by Inventor Carmelo Paolino
Carmelo Paolino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10593410Abstract: A sense-amplifier circuit can be used with a non-volatile memory device having a memory array with memory cells arranged in word lines and bit lines and coupled to respective source lines. The circuit has a first circuit branch and a second circuit branch, which receive on a respective first comparison input and second comparison input, during a reading step of a datum stored in a memory cell, a cell current from the bit line associated to the memory cell and a reference current, from a reference bit line in a differential reading operation or from a current-reference generator in a single-ended reading operation. The first and second circuit branches generate, during the datum-reading step, a first output voltage and a second output voltage, as a function of the difference between the cell current and the reference current.Type: GrantFiled: September 28, 2018Date of Patent: March 17, 2020Assignee: STMicroelectronics S.r.l.Inventors: Carmelo Paolino, Antonino Conte, Anna Rita Maria Lipani
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Publication number: 20190108886Abstract: A sense-amplifier circuit can be used with a non-volatile memory device having a memory array with memory cells arranged in word lines and bit lines and coupled to respective source lines. The circuit has a first circuit branch and a second circuit branch, which receive on a respective first comparison input and second comparison input, during a reading step of a datum stored in a memory cell, a cell current from the bit line associated to the memory cell and a reference current, from a reference bit line in a differential reading operation or from a current-reference generator in a single-ended reading operation. The first and second circuit branches generate, during the datum-reading step, a first output voltage and a second output voltage, as a function of the difference between the cell current and the reference current.Type: ApplicationFiled: September 28, 2018Publication date: April 11, 2019Inventors: Carmelo Paolino, Antonino Conte, Anna Rita Maria Lipani
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Patent number: 10186317Abstract: A phase change memory device includes two portions with local bitlines connected to memory cells. A reading stage is configured to read logic data stored by the first and second memory cells. A first main bitline extends between the reading stage and the first local bitlines and a first main switch is coupled between the first main bitline and reading stage and likewise for the second portion. Local switches are associated with respective ones of the local bitlines. A first reference signal generator is coupled to the reading stage. The phase change memory device is configured to operate in a first reading mode, in which the logic data stored by the first memory cell is read by the reading stage by comparison with the reference signal.Type: GrantFiled: December 14, 2017Date of Patent: January 22, 2019Assignee: STMicroelectronics S.r.l.Inventors: Maurizio Francesco Perroni, Carmelo Paolino, Salvatore Polizzi
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Patent number: 9972394Abstract: A level shifter circuit is designed to shift an input signal that switches within a first voltage range to supply an output signal that switches within a second voltage range, higher than the first voltage range. A first inverter stage has an input receiving the input signal and also has an output. A first capacitive element is connected between the output of the first input inverter stage and a first holding node. A latch stage is connected between the first holding node and a second holding node that is coupled to an output terminal, on which the output signal is present. The first input inverter stage is designed to operate in the first voltage range, and the latch stage is designed to operate in the second voltage range.Type: GrantFiled: March 31, 2017Date of Patent: May 15, 2018Assignee: STMicroelectronics S.r.l.Inventors: Antonino Conte, Carmelo Paolino, Maurizio Francesco Perroni, Salvatore Polizzi
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Patent number: 9964976Abstract: A voltage-regulator device includes an error-amplifier stage configured to receive a first reference voltage and a feedback voltage, an output amplifier stage coupled to the error-amplifier stage and configured to generate an output voltage related to the first reference voltage by an amplification factor, and a feedback stage configured to generate the feedback voltage. A compensation stage is configured to implement a second feedback loop, and cause, in response to a variation of the output voltage, a corresponding variation of a first biasing voltage for the output amplifier stage. The compensation stage includes a coupling-capacitor element coupled between the output amplifier stage and a first internal node, and a driving module coupled between the first internal node, and the output amplifier stage and configured to generate a compensation voltage for driving the output amplifier stage.Type: GrantFiled: May 16, 2017Date of Patent: May 8, 2018Assignee: STMICROELECTRONICS S.R.L.Inventors: Antonino Conte, Carmelo Paolino
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Publication number: 20180108405Abstract: A phase change memory device includes two portions with local bitlines connected to memory cells. A reading stage is configured to read logic data stored by the first and second memory cells. A first main bitline extends between the reading stage and the first local bitlines and a first main switch is coupled between the first main bitline and reading stage and likewise for the second portion. Local switches are associated with respective ones of the local bitlines. A first reference signal generator is coupled to the reading stage. The phase change memory device is configured to operate in a first reading mode, in which the logic data stored by the first memory cell is read by the reading stage by comparison with the reference signal.Type: ApplicationFiled: December 14, 2017Publication date: April 19, 2018Inventors: Maurizio Francesco Perroni, Carmelo Paolino, Salvatore Polizzi
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Publication number: 20180061495Abstract: A level shifter circuit is designed to shift an input signal that switches within a first voltage range to supply an output signal that switches within a second voltage range, higher than the first voltage range. A first inverter stage has an input receiving the input signal and also has an output. A first capacitive element is connected between the output of the first input inverter stage and a first holding node. A latch stage is connected between the first holding node and a second holding node that is coupled to an output terminal, on which the output signal is present. The first input inverter stage is designed to operate in the first voltage range, and the latch stage is designed to operate in the second voltage range.Type: ApplicationFiled: March 31, 2017Publication date: March 1, 2018Inventors: Antonino Conte, Carmelo Paolino, Maurizio Francesco Perroni, Salvatore Polizzi
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Patent number: 9865346Abstract: A phase change memory device includes two portions with local bitlines connected to memory cells. A reading stage is configured to read logic data stored by the first and second memory cells. A first main bitline extends between the reading stage and the first local bitlines and a first main switch is coupled between the first main bitline and reading stage and likewise for the second portion. Local switches are associated with respective ones of the local bitlines. A first reference signal generator is coupled to the reading stage. The phase change memory device is configured to operate in a first reading mode, in which the logic data stored by the first memory cell is read by the reading stage by comparison with the reference signal.Type: GrantFiled: March 31, 2017Date of Patent: January 9, 2018Assignee: STMicroelectronics S.r.l.Inventors: Maurizio Francesco Perroni, Carmelo Paolino, Salvatore Polizzi
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Publication number: 20170248981Abstract: A voltage-regulator device includes an error-amplifier stage configured to receive a first reference voltage and a feedback voltage, an output amplifier stage coupled to the error-amplifier stage and configured to generate an output voltage related to the first reference voltage by an amplification factor, and a feedback stage configured to generate the feedback voltage. A compensation stage is configured to implement a second feedback loop, and cause, in response to a variation of the output voltage, a corresponding variation of a first biasing voltage for the output amplifier stage. The compensation stage includes a coupling-capacitor element coupled between the output amplifier stage and a first internal node, and a driving module coupled between the first internal node, and the output amplifier stage and configured to generate a compensation voltage for driving the output amplifier stage.Type: ApplicationFiled: May 16, 2017Publication date: August 31, 2017Inventors: Antonino Conte, Carmelo Paolino
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Patent number: 9684324Abstract: A voltage-regulator device includes an error-amplifier stage configured to receive a first reference voltage and a feedback voltage, an output amplifier stage coupled to the error-amplifier stage and configured to generate an output voltage related to the first reference voltage by an amplification factor, and a feedback stage configured to generate the feedback voltage. A compensation stage is configured to implement a second feedback loop, and cause, in response to a variation of the output voltage, a corresponding variation of a first biasing voltage for the output amplifier stage. The compensation stage includes a coupling-capacitor element coupled between the output amplifier stage and a first internal node, and a driving module coupled between the first internal node, and the output amplifier stage and configured to generate a compensation voltage for driving the output amplifier stage.Type: GrantFiled: December 15, 2015Date of Patent: June 20, 2017Assignee: STMICROELECTRONICS S.R.L.Inventors: Antonino Conte, Carmelo Paolino
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Publication number: 20160349776Abstract: A voltage-regulator device includes an error-amplifier stage configured to receive a first reference voltage and a feedback voltage, an output amplifier stage coupled to the error-amplifier stage and configured to generate an output voltage related to the first reference voltage by an amplification factor, and a feedback stage configured to generate the feedback voltage. A compensation stage is configured to implement a second feedback loop, and cause, in response to a variation of the output voltage, a corresponding variation of a first biasing voltage for the output amplifier stage. The compensation stage includes a coupling-capacitor element coupled between the output amplifier stage and a first internal node, and a driving module coupled between the first internal node, and the output amplifier stage and configured to generate a compensation voltage for driving the output amplifier stage.Type: ApplicationFiled: December 15, 2015Publication date: December 1, 2016Inventors: Antonino CONTE, Carmelo PAOLINO
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Patent number: 6075718Abstract: The method comprises the steps of detecting the trailing edge of an initialization signal, and generating a read bias signal and a read activation signal for the cell, when the trailing edge of the initialization signal is detected. The signals of read bias and read activation have a ramp-like leading edge and both signals are disabled when reading of the cell is completed. Thereby, phenomena of soft-writing of the cell are avoided, and risks of erroneous readings are reduced.Type: GrantFiled: March 16, 1998Date of Patent: June 13, 2000Assignee: STMicroelectronics, S.r.l.Inventors: Marco Fontana, Antonio Barcella, Massimo Montanaro, Carmelo Paolino