Patents by Inventor Caroline D. Benveniste

Caroline D. Benveniste has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6779088
    Abstract: A compressed memory system includes a cache, and compressed memory including fixed size storage blocks for storing both compressed data segments and fixed size storage blocks defining a virtual uncompressed cache (VUC) for storing uncompressed data segments to enable reduced data access latency. The compressed memory system implements a system and method for controlling the size of the VUC so as to optimize system performance in a manner which permits the avoidance of operating system intervention which is required in certain circumstances for correct system operation. The system solves-these problems by implementing one or more thresholds, which may be set by the operating system, but which, after being sets control the size of the VUC independently of the operating system or other system software.
    Type: Grant
    Filed: October 24, 2000
    Date of Patent: August 17, 2004
    Assignee: International Business Machines Corporation
    Inventors: Caroline D. Benveniste, Peter A. Franaszek, John T. Robinson
  • Patent number: 6587923
    Abstract: In a computer system having a processor, a memory system including multiple levels of caches L1, L2, . . . , Ln−1 and including main memory Ln, and in which the cache Li−1 includes lines of size s and the cache Li includes lines of size t with t>s, a dual line size cache directory mechanism, in which the contents of a cache Li−1 may be accessed at line size granularity s (in which case it is determined whether a line corresponding to a given memory address is stored in Li−1, and if so its location and status), and in which the contents of Li−1 may also be accessed at line size granularity t (in which case it is determined whether any of the t/s lines of size s residing in the larger line of size t corresponding to a given memory address are stored in Li−1, and if so their locations and status) without multiple sequential accesses to a cache Li−1 directory structure.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: July 1, 2003
    Assignee: International Business Machines Corporation
    Inventors: Caroline D. Benveniste, Peter A. Franaszek, John T. Robinson
  • Patent number: 6353871
    Abstract: A system including a CPU, memory, and compression controller hardware, and implementing a first directory structure included in a first memory wherein CPU generated real memory addresses are translated into one or more physical memory locations using the first directory structure, further includes a second directory cache structure having entries corresponding to directory entries included in the first directory structure. In a first embodiment, the second directory cache structure is implemented as part of compression controller hardware. In a second embodiment, a common directory and cache memory structure is provided for storing a subset of directory entries in the directory structure together with a subset of the memory contents.
    Type: Grant
    Filed: February 22, 1999
    Date of Patent: March 5, 2002
    Assignee: International Business Machines Corporation
    Inventors: Caroline D. Benveniste, Peter A. Franaszek, John T. Robinson, Charles O. Schulz
  • Patent number: 6349372
    Abstract: System and method for reducing data access latency for cache miss operations in a computer system implementing main memory compression in which the unit of compression is a memory segment. The method includes steps of providing common memory area in main memory for storing compressed and uncompressed data segments; accessing directory structure formed in the main memory having entries for locating both uncompressed data segments and compressed data segments for cache miss operations, each directory entry including index for locating data segments in the main memory and further indicating status of the data segment; and, checking a status indication of a data segment to be accessed for a cache miss operation, and processing either a compressed or uncompressed data segment from the common memory area according to the status.
    Type: Grant
    Filed: May 19, 1999
    Date of Patent: February 19, 2002
    Assignee: International Business Machines Corporation
    Inventors: Caroline D. Benveniste, Peter A. Franaszek, John T. Robinson, Charles O. Schulz